sim_object.hh revision 13781:280e5206fd97
12SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2015 ARM Limited 39920Syasuko.eckert@amd.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 147338SAli.Saidi@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 151762SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc. 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422SN/A * Nathan Binkert 432SN/A */ 4411793Sbrandon.potter@amd.com 4511793Sbrandon.potter@amd.com/* @file 468779Sgblack@eecs.umich.edu * User Console Definitions 478779Sgblack@eecs.umich.edu */ 488779Sgblack@eecs.umich.edu 492439SN/A#ifndef __SIM_OBJECT_HH__ 508779Sgblack@eecs.umich.edu#define __SIM_OBJECT_HH__ 516216Snate@binkert.org 52146SN/A#include <string> 53146SN/A#include <vector> 5411793Sbrandon.potter@amd.com 55146SN/A#include "params/SimObject.hh" 56146SN/A#include "sim/drain.hh" 57146SN/A#include "sim/eventq.hh" 586216Snate@binkert.org#include "sim/eventq_impl.hh" 596658Snate@binkert.org#include "sim/port.hh" 601717SN/A#include "sim/serialize.hh" 618887Sgeoffrey.blake@arm.com 628887Sgeoffrey.blake@arm.comclass EventManager; 63146SN/Aclass ProbeManager; 6410061Sandreas@sandberg.pp.se 651977SN/A/** 6611147Smitch.hayenga@arm.com * Abstract superclass for simulation objects. Represents things that 672683Sktlim@umich.edu * correspond to physical components and can be specified via the 681717SN/A * config file (CPUs, caches, etc.). 69146SN/A * 702683Sktlim@umich.edu * SimObject initialization is controlled by the instantiate method in 718232Snate@binkert.org * src/python/m5/simulate.py. There are slightly different 728232Snate@binkert.org * initialization paths when starting the simulation afresh and when 738232Snate@binkert.org * loading from a checkpoint. After instantiation and connecting 748779Sgblack@eecs.umich.edu * ports, simulate.py initializes the object using the following call 753348Sbinkertn@umich.edu * sequence: 766105Ssteve.reinhardt@amd.com * 776216Snate@binkert.org * <ol> 782036SN/A * <li>SimObject::init() 79146SN/A * <li>SimObject::regStats() 808817Sgblack@eecs.umich.edu * <li><ul> 818793Sgblack@eecs.umich.edu * <li>SimObject::initState() if starting afresh. 8256SN/A * <li>SimObject::loadState() if restoring from a checkpoint. 8356SN/A * </ul> 84695SN/A * <li>SimObject::resetStats() 852901Ssaidi@eecs.umich.edu * <li>SimObject::startup() 862SN/A * <li>Drainable::drainResume() if resuming from a checkpoint. 872SN/A * </ol> 882449SN/A * 891355SN/A * @note Whenever a method is called on all objects in the simulator's 905529Snate@binkert.org * object tree (e.g., init(), startup(), or loadState()), a pre-order 9110061Sandreas@sandberg.pp.se * depth-first traversal is performed (see descendants() in 9211147Smitch.hayenga@arm.com * SimObject.py). This has the effect of calling the method on the 9310061Sandreas@sandberg.pp.se * parent node <i>before</i> its children. 9411147Smitch.hayenga@arm.com */ 9511147Smitch.hayenga@arm.comclass SimObject : public EventManager, public Serializable, public Drainable 9611147Smitch.hayenga@arm.com{ 97224SN/A private: 9811147Smitch.hayenga@arm.com typedef std::vector<SimObject *> SimObjectList; 992SN/A 10011147Smitch.hayenga@arm.com /** List of all instantiated simulation objects. */ 10111147Smitch.hayenga@arm.com static SimObjectList simObjectList; 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com /** Manager coordinates hooking up probe points with listeners. */ 10411147Smitch.hayenga@arm.com ProbeManager *probeManager; 10511147Smitch.hayenga@arm.com 10611147Smitch.hayenga@arm.com protected: 10711147Smitch.hayenga@arm.com /** Cached copy of the object parameters. */ 10811147Smitch.hayenga@arm.com const SimObjectParams *_params; 10911147Smitch.hayenga@arm.com 11011147Smitch.hayenga@arm.com public: 11111147Smitch.hayenga@arm.com typedef SimObjectParams Params; 1122SN/A const Params *params() const { return _params; } 1138733Sgeoffrey.blake@arm.com SimObject(const Params *_params); 11411147Smitch.hayenga@arm.com virtual ~SimObject(); 11511147Smitch.hayenga@arm.com 11611147Smitch.hayenga@arm.com public: 1178733Sgeoffrey.blake@arm.com 1188733Sgeoffrey.blake@arm.com virtual const std::string name() const { return params()->name; } 1198733Sgeoffrey.blake@arm.com 1208733Sgeoffrey.blake@arm.com /** 12111147Smitch.hayenga@arm.com * init() is called after all C++ SimObjects have been created and 12211147Smitch.hayenga@arm.com * all ports are connected. Initializations that are independent 1238733Sgeoffrey.blake@arm.com * of unserialization but rely on a fully instantiated and 1248733Sgeoffrey.blake@arm.com * connected SimObject graph should be done here. 1258733Sgeoffrey.blake@arm.com */ 12611147Smitch.hayenga@arm.com virtual void init(); 1278733Sgeoffrey.blake@arm.com 12811147Smitch.hayenga@arm.com /** 12911147Smitch.hayenga@arm.com * loadState() is called on each SimObject when restoring from a 13011147Smitch.hayenga@arm.com * checkpoint. The default implementation simply calls 13111147Smitch.hayenga@arm.com * unserialize() if there is a corresponding section in the 1322SN/A * checkpoint. However, objects can override loadState() to get 13311147Smitch.hayenga@arm.com * other behaviors, e.g., doing other programmed initializations 13411147Smitch.hayenga@arm.com * after unserialize(), or complaining if no checkpoint section is 13511147Smitch.hayenga@arm.com * found. 1364377Sgblack@eecs.umich.edu * 13711147Smitch.hayenga@arm.com * @param cp Checkpoint to restore the state from. 13811147Smitch.hayenga@arm.com */ 13911147Smitch.hayenga@arm.com virtual void loadState(CheckpointIn &cp); 14011147Smitch.hayenga@arm.com 14111147Smitch.hayenga@arm.com /** 14211147Smitch.hayenga@arm.com * initState() is called on each SimObject when *not* restoring 1435169Ssaidi@eecs.umich.edu * from a checkpoint. This provides a hook for state 14411147Smitch.hayenga@arm.com * initializations that are only required for a "cold start". 14511147Smitch.hayenga@arm.com */ 14611147Smitch.hayenga@arm.com virtual void initState(); 14711147Smitch.hayenga@arm.com 14811147Smitch.hayenga@arm.com /** 14911147Smitch.hayenga@arm.com * Register statistics for this object. 15011147Smitch.hayenga@arm.com */ 15111147Smitch.hayenga@arm.com virtual void regStats(); 15211147Smitch.hayenga@arm.com 15311147Smitch.hayenga@arm.com /** 15411147Smitch.hayenga@arm.com * Reset statistics associated with this object. 15511147Smitch.hayenga@arm.com */ 15611147Smitch.hayenga@arm.com virtual void resetStats(); 15711147Smitch.hayenga@arm.com 15811147Smitch.hayenga@arm.com /** 15911147Smitch.hayenga@arm.com * Register probe points for this object. 16011147Smitch.hayenga@arm.com */ 16111147Smitch.hayenga@arm.com virtual void regProbePoints(); 16211147Smitch.hayenga@arm.com 16311147Smitch.hayenga@arm.com /** 16411147Smitch.hayenga@arm.com * Register probe listeners for this object. 16511147Smitch.hayenga@arm.com */ 16611147Smitch.hayenga@arm.com virtual void regProbeListeners(); 16711147Smitch.hayenga@arm.com 16811147Smitch.hayenga@arm.com /** 16911147Smitch.hayenga@arm.com * Get the probe manager for this object. 17011147Smitch.hayenga@arm.com */ 17111147Smitch.hayenga@arm.com ProbeManager *getProbeManager(); 17211147Smitch.hayenga@arm.com 17311147Smitch.hayenga@arm.com /** 17411147Smitch.hayenga@arm.com * Get a port with a given name and index. This is used at binding time 17511147Smitch.hayenga@arm.com * and returns a reference to a protocol-agnostic port. 17611147Smitch.hayenga@arm.com * 17711147Smitch.hayenga@arm.com * @param if_name Port name 17811147Smitch.hayenga@arm.com * @param idx Index in the case of a VectorPort 17911147Smitch.hayenga@arm.com * 18011147Smitch.hayenga@arm.com * @return A reference to the given port 18111147Smitch.hayenga@arm.com */ 18211147Smitch.hayenga@arm.com virtual Port &getPort(const std::string &if_name, 18311147Smitch.hayenga@arm.com PortID idx=InvalidPortID); 18411147Smitch.hayenga@arm.com 18511147Smitch.hayenga@arm.com /** 18611147Smitch.hayenga@arm.com * startup() is the final initialization call before simulation. 18711147Smitch.hayenga@arm.com * All state is initialized (including unserialized state, if any, 18811147Smitch.hayenga@arm.com * such as the curTick() value), so this is the appropriate place to 18911147Smitch.hayenga@arm.com * schedule initial event(s) for objects that need them. 19011147Smitch.hayenga@arm.com */ 19111147Smitch.hayenga@arm.com virtual void startup(); 19211147Smitch.hayenga@arm.com 19311147Smitch.hayenga@arm.com /** 19411147Smitch.hayenga@arm.com * Provide a default implementation of the drain interface for 19511147Smitch.hayenga@arm.com * objects that don't need draining. 19611147Smitch.hayenga@arm.com */ 19711147Smitch.hayenga@arm.com DrainState drain() override { return DrainState::Drained; } 19811147Smitch.hayenga@arm.com 19911147Smitch.hayenga@arm.com /** 20011147Smitch.hayenga@arm.com * Write back dirty buffers to memory using functional writes. 20111147Smitch.hayenga@arm.com * 20211147Smitch.hayenga@arm.com * After returning, an object implementing this method should have 20311147Smitch.hayenga@arm.com * written all its dirty data back to memory. This method is 20411147Smitch.hayenga@arm.com * typically used to prepare a system with caches for 20511147Smitch.hayenga@arm.com * checkpointing. 20611147Smitch.hayenga@arm.com */ 2072SN/A virtual void memWriteback() {}; 2082SN/A 2092623SN/A /** 2102SN/A * Invalidate the contents of memory buffers. 2112SN/A * 2122SN/A * When the switching to hardware virtualized CPU models, we need 213180SN/A * to make sure that we don't have any cached state in the system 2148737Skoansin.tan@gmail.com * that might become stale when we return. This method is used to 215393SN/A * flush all such state back to main memory. 216393SN/A * 217393SN/A * @warn This does <i>not</i> cause any dirty state to be written 218393SN/A * back to memory. 219384SN/A */ 220189SN/A virtual void memInvalidate() {}; 221189SN/A 2222623SN/A void serialize(CheckpointOut &cp) const override {}; 2232SN/A void unserialize(CheckpointIn &cp) override {}; 224729SN/A 225334SN/A /** 2262SN/A * Serialize all SimObjects in the system. 2272SN/A */ 22811147Smitch.hayenga@arm.com static void serializeAll(CheckpointOut &cp); 22911147Smitch.hayenga@arm.com 2308834Satgutier@umich.edu#ifdef DEBUG 23111147Smitch.hayenga@arm.com public: 23211147Smitch.hayenga@arm.com bool doDebugBreak; 23311147Smitch.hayenga@arm.com static void debugObjectBreak(const std::string &objs); 2342SN/A#endif 23511147Smitch.hayenga@arm.com 23611147Smitch.hayenga@arm.com /** 23711147Smitch.hayenga@arm.com * Find the SimObject with the given name and return a pointer to 23811147Smitch.hayenga@arm.com * it. Primarily used for interactive debugging. Argument is 2397897Shestness@cs.utexas.edu * char* rather than std::string to make it callable from gdb. 24011147Smitch.hayenga@arm.com */ 24111147Smitch.hayenga@arm.com static SimObject *find(const char *name); 24211147Smitch.hayenga@arm.com}; 24311147Smitch.hayenga@arm.com 2447897Shestness@cs.utexas.edu/** 24511147Smitch.hayenga@arm.com * Base class to wrap object resolving functionality. 24611147Smitch.hayenga@arm.com * 24711147Smitch.hayenga@arm.com * This can be provided to the serialization framework to allow it to 24811147Smitch.hayenga@arm.com * map object names onto C++ objects. 2497897Shestness@cs.utexas.edu */ 25011147Smitch.hayenga@arm.comclass SimObjectResolver 25111147Smitch.hayenga@arm.com{ 25211147Smitch.hayenga@arm.com public: 25311147Smitch.hayenga@arm.com virtual ~SimObjectResolver() { } 2547897Shestness@cs.utexas.edu 25511147Smitch.hayenga@arm.com // Find a SimObject given a full path name 25611147Smitch.hayenga@arm.com virtual SimObject *resolveSimObject(const std::string &name) = 0; 25711147Smitch.hayenga@arm.com}; 25811147Smitch.hayenga@arm.com 2597897Shestness@cs.utexas.edu#ifdef DEBUG 26011147Smitch.hayenga@arm.comvoid debugObjectBreak(const char *objs); 26111147Smitch.hayenga@arm.com#endif 26211147Smitch.hayenga@arm.com 26311147Smitch.hayenga@arm.com#endif // __SIM_OBJECT_HH__ 2647897Shestness@cs.utexas.edu