sim_object.cc revision 7534
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 37534Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 336216Snate@binkert.org#include <cassert> 342SN/A 35330SN/A#include "base/callback.hh" 3656SN/A#include "base/inifile.hh" 371031SN/A#include "base/match.hh" 38330SN/A#include "base/misc.hh" 39330SN/A#include "base/trace.hh" 406214Snate@binkert.org#include "base/types.hh" 41330SN/A#include "sim/sim_object.hh" 42695SN/A#include "sim/stats.hh" 432SN/A 442SN/Ausing namespace std; 452SN/A 462SN/A 472SN/A//////////////////////////////////////////////////////////////////////// 482SN/A// 492SN/A// SimObject member definitions 502SN/A// 512SN/A//////////////////////////////////////////////////////////////////////// 522SN/A 532SN/A// 542SN/A// static list of all SimObjects, used for initialization etc. 552SN/A// 562SN/ASimObject::SimObjectList SimObject::simObjectList; 572SN/A 582SN/A// 592SN/A// SimObject constructor: used to maintain static simObjectList 602SN/A// 614762Snate@binkert.orgSimObject::SimObject(const Params *p) 625605Snate@binkert.org : EventManager(p->eventq), _params(p) 632SN/A{ 641031SN/A#ifdef DEBUG 651031SN/A doDebugBreak = false; 661031SN/A#endif 671031SN/A 681553SN/A simObjectList.push_back(this); 692901Ssaidi@eecs.umich.edu state = Running; 701553SN/A} 711553SN/A 72465SN/Avoid 73465SN/ASimObject::init() 74465SN/A{ 75465SN/A} 76465SN/A 777492Ssteve.reinhardt@amd.comvoid 787532Ssteve.reinhardt@amd.comSimObject::loadState(Checkpoint *cp) 797532Ssteve.reinhardt@amd.com{ 807532Ssteve.reinhardt@amd.com if (cp->sectionExists(name())) 817532Ssteve.reinhardt@amd.com unserialize(cp, name()); 827532Ssteve.reinhardt@amd.com} 837532Ssteve.reinhardt@amd.com 847532Ssteve.reinhardt@amd.comvoid 857532Ssteve.reinhardt@amd.comSimObject::initState() 867532Ssteve.reinhardt@amd.com{ 877532Ssteve.reinhardt@amd.com} 887532Ssteve.reinhardt@amd.com 897532Ssteve.reinhardt@amd.comvoid 907492Ssteve.reinhardt@amd.comSimObject::startup() 917492Ssteve.reinhardt@amd.com{ 927492Ssteve.reinhardt@amd.com} 937492Ssteve.reinhardt@amd.com 942SN/A// 952SN/A// no default statistics, so nothing to do in base implementation 962SN/A// 972SN/Avoid 982SN/ASimObject::regStats() 992SN/A{ 1002SN/A} 1012SN/A 1022SN/Avoid 1032SN/ASimObject::regFormulas() 1042SN/A{ 1052SN/A} 1062SN/A 107330SN/Avoid 108330SN/ASimObject::resetStats() 109330SN/A{ 110330SN/A} 111330SN/A 1122SN/A// 113395SN/A// static function: serialize all SimObjects. 114395SN/A// 115395SN/Avoid 116395SN/ASimObject::serializeAll(ostream &os) 117395SN/A{ 118573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 119573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 120395SN/A 121573SN/A for (; ri != rend; ++ri) { 122573SN/A SimObject *obj = *ri; 123395SN/A obj->nameOut(os); 124395SN/A obj->serialize(os); 125395SN/A } 126395SN/A} 127843SN/A 1282797Sktlim@umich.eduvoid 1292797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp) 1302797Sktlim@umich.edu{ 1312797Sktlim@umich.edu SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 1322797Sktlim@umich.edu SimObjectList::reverse_iterator rend = simObjectList.rend(); 1332797Sktlim@umich.edu 1342797Sktlim@umich.edu for (; ri != rend; ++ri) { 1352797Sktlim@umich.edu SimObject *obj = *ri; 1362797Sktlim@umich.edu DPRINTFR(Config, "Unserializing '%s'\n", 1372797Sktlim@umich.edu obj->name()); 1382797Sktlim@umich.edu if(cp->sectionExists(obj->name())) 1392797Sktlim@umich.edu obj->unserialize(cp, obj->name()); 1402797Sktlim@umich.edu else 1412797Sktlim@umich.edu warn("Not unserializing '%s': no section found in checkpoint.\n", 1422797Sktlim@umich.edu obj->name()); 1432797Sktlim@umich.edu } 1442797Sktlim@umich.edu} 1452797Sktlim@umich.edu 1467492Ssteve.reinhardt@amd.com 1477492Ssteve.reinhardt@amd.com 1481031SN/A#ifdef DEBUG 1491031SN/A// 1501031SN/A// static function: flag which objects should have the debugger break 1511031SN/A// 1521031SN/Avoid 1531031SN/ASimObject::debugObjectBreak(const string &objs) 1541031SN/A{ 1551031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 1561031SN/A SimObjectList::const_iterator end = simObjectList.end(); 1571031SN/A 1581031SN/A ObjectMatch match(objs); 1591031SN/A for (; i != end; ++i) { 1601031SN/A SimObject *obj = *i; 1611031SN/A obj->doDebugBreak = match.match(obj->name()); 1621031SN/A } 1631031SN/A} 1641031SN/A 1651031SN/Avoid 1661031SN/AdebugObjectBreak(const char *objs) 1671031SN/A{ 1681031SN/A SimObject::debugObjectBreak(string(objs)); 1691031SN/A} 1701031SN/A#endif 1711031SN/A 1722901Ssaidi@eecs.umich.eduunsigned int 1732839Sktlim@umich.eduSimObject::drain(Event *drain_event) 1742797Sktlim@umich.edu{ 1752901Ssaidi@eecs.umich.edu state = Drained; 1762901Ssaidi@eecs.umich.edu return 0; 1772797Sktlim@umich.edu} 1782797Sktlim@umich.edu 1792609SN/Avoid 1802797Sktlim@umich.eduSimObject::resume() 1812609SN/A{ 1822901Ssaidi@eecs.umich.edu state = Running; 1832797Sktlim@umich.edu} 1842797Sktlim@umich.edu 1852797Sktlim@umich.eduvoid 1862797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode) 1872797Sktlim@umich.edu{ 1882901Ssaidi@eecs.umich.edu panic("setMemoryMode() should only be called on systems"); 1892797Sktlim@umich.edu} 1902797Sktlim@umich.edu 1912797Sktlim@umich.eduvoid 1922797Sktlim@umich.eduSimObject::switchOut() 1932797Sktlim@umich.edu{ 1942797Sktlim@umich.edu panic("Unimplemented!"); 1952797Sktlim@umich.edu} 1962797Sktlim@umich.edu 1972797Sktlim@umich.eduvoid 1982797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu) 1992797Sktlim@umich.edu{ 2002797Sktlim@umich.edu panic("Unimplemented!"); 2012609SN/A} 2025314Sstever@gmail.com 2035314Sstever@gmail.com 2045314Sstever@gmail.comSimObject * 2055314Sstever@gmail.comSimObject::find(const char *name) 2065314Sstever@gmail.com{ 2075314Sstever@gmail.com SimObjectList::const_iterator i = simObjectList.begin(); 2085314Sstever@gmail.com SimObjectList::const_iterator end = simObjectList.end(); 2095314Sstever@gmail.com 2105314Sstever@gmail.com for (; i != end; ++i) { 2115314Sstever@gmail.com SimObject *obj = *i; 2125314Sstever@gmail.com if (obj->name() == name) 2135314Sstever@gmail.com return obj; 2145314Sstever@gmail.com } 2155314Sstever@gmail.com 2165314Sstever@gmail.com return NULL; 2175314Sstever@gmail.com} 218