sim_object.cc revision 4762
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include <assert.h> 332SN/A 34330SN/A#include "base/callback.hh" 3556SN/A#include "base/inifile.hh" 361031SN/A#include "base/match.hh" 37330SN/A#include "base/misc.hh" 38330SN/A#include "base/trace.hh" 39938SN/A#include "base/stats/events.hh" 4056SN/A#include "sim/host.hh" 41330SN/A#include "sim/sim_object.hh" 42695SN/A#include "sim/stats.hh" 432SN/A 442SN/Ausing namespace std; 452SN/A 462SN/A 472SN/A//////////////////////////////////////////////////////////////////////// 482SN/A// 492SN/A// SimObject member definitions 502SN/A// 512SN/A//////////////////////////////////////////////////////////////////////// 522SN/A 532SN/A// 542SN/A// static list of all SimObjects, used for initialization etc. 552SN/A// 562SN/ASimObject::SimObjectList SimObject::simObjectList; 572SN/A 582SN/A// 592SN/A// SimObject constructor: used to maintain static simObjectList 602SN/A// 614762Snate@binkert.orgSimObject::SimObject(const Params *p) 621553SN/A : _params(p) 632SN/A{ 641031SN/A#ifdef DEBUG 651031SN/A doDebugBreak = false; 661031SN/A#endif 671031SN/A 681553SN/A simObjectList.push_back(this); 692901Ssaidi@eecs.umich.edu state = Running; 701553SN/A} 711553SN/A 724762Snate@binkert.orgSimObjectParams * 734762Snate@binkert.orgmakeParams(const string &name) 744762Snate@binkert.org{ 754762Snate@binkert.org SimObjectParams *params = new SimObjectParams; 764762Snate@binkert.org params->name = name; 774762Snate@binkert.org 784762Snate@binkert.org return params; 794762Snate@binkert.org} 804762Snate@binkert.org 811553SN/ASimObject::SimObject(const string &_name) 824762Snate@binkert.org : _params(makeParams(_name)) 831553SN/A{ 841553SN/A#ifdef DEBUG 851553SN/A doDebugBreak = false; 861553SN/A#endif 871553SN/A 882SN/A simObjectList.push_back(this); 892901Ssaidi@eecs.umich.edu state = Running; 902SN/A} 912SN/A 92465SN/Avoid 93465SN/ASimObject::init() 94465SN/A{ 95465SN/A} 96465SN/A 972SN/A// 982SN/A// no default statistics, so nothing to do in base implementation 992SN/A// 1002SN/Avoid 1012SN/ASimObject::regStats() 1022SN/A{ 1032SN/A} 1042SN/A 1052SN/Avoid 1062SN/ASimObject::regFormulas() 1072SN/A{ 1082SN/A} 1092SN/A 110330SN/Avoid 111330SN/ASimObject::resetStats() 112330SN/A{ 113330SN/A} 114330SN/A 1152SN/A// 11653SN/A// static function: 11753SN/A// call regStats() on all SimObjects and then regFormulas() on all 11853SN/A// SimObjects. 1192SN/A// 120334SN/Astruct SimObjectResetCB : public Callback 121334SN/A{ 122334SN/A virtual void process() { SimObject::resetAllStats(); } 123334SN/A}; 124334SN/A 125334SN/Anamespace { 126334SN/A static SimObjectResetCB StatResetCB; 127334SN/A} 128334SN/A 1292SN/Avoid 1302SN/ASimObject::regAllStats() 1312SN/A{ 1322SN/A SimObjectList::iterator i; 1332SN/A SimObjectList::iterator end = simObjectList.end(); 1342SN/A 1352SN/A /** 1362SN/A * @todo change cprintfs to DPRINTFs 1372SN/A */ 1382SN/A for (i = simObjectList.begin(); i != end; ++i) { 1392SN/A#ifdef STAT_DEBUG 1402SN/A cprintf("registering stats for %s\n", (*i)->name()); 1412SN/A#endif 1422SN/A (*i)->regStats(); 1432SN/A } 1442SN/A 1452SN/A for (i = simObjectList.begin(); i != end; ++i) { 1462SN/A#ifdef STAT_DEBUG 1472SN/A cprintf("registering formulas for %s\n", (*i)->name()); 1482SN/A#endif 1492SN/A (*i)->regFormulas(); 150334SN/A } 151334SN/A 152729SN/A Stats::registerResetCallback(&StatResetCB); 1532SN/A} 1542SN/A 1552SN/A// 156465SN/A// static function: call init() on all SimObjects. 157465SN/A// 158465SN/Avoid 159465SN/ASimObject::initAll() 160465SN/A{ 161465SN/A SimObjectList::iterator i = simObjectList.begin(); 162465SN/A SimObjectList::iterator end = simObjectList.end(); 163465SN/A 164465SN/A for (; i != end; ++i) { 165465SN/A SimObject *obj = *i; 166465SN/A obj->init(); 167465SN/A } 168465SN/A} 169465SN/A 170465SN/A// 171330SN/A// static function: call resetStats() on all SimObjects. 172330SN/A// 173330SN/Avoid 174330SN/ASimObject::resetAllStats() 175330SN/A{ 176332SN/A SimObjectList::iterator i = simObjectList.begin(); 177332SN/A SimObjectList::iterator end = simObjectList.end(); 178332SN/A 179332SN/A for (; i != end; ++i) { 180332SN/A SimObject *obj = *i; 181332SN/A obj->resetStats(); 182332SN/A } 183330SN/A} 184330SN/A 185330SN/A// 186395SN/A// static function: serialize all SimObjects. 187395SN/A// 188395SN/Avoid 189395SN/ASimObject::serializeAll(ostream &os) 190395SN/A{ 191573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 192573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 193395SN/A 194573SN/A for (; ri != rend; ++ri) { 195573SN/A SimObject *obj = *ri; 196395SN/A obj->nameOut(os); 197395SN/A obj->serialize(os); 198395SN/A } 199395SN/A} 200843SN/A 2012797Sktlim@umich.eduvoid 2022797Sktlim@umich.eduSimObject::unserializeAll(Checkpoint *cp) 2032797Sktlim@umich.edu{ 2042797Sktlim@umich.edu SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 2052797Sktlim@umich.edu SimObjectList::reverse_iterator rend = simObjectList.rend(); 2062797Sktlim@umich.edu 2072797Sktlim@umich.edu for (; ri != rend; ++ri) { 2082797Sktlim@umich.edu SimObject *obj = *ri; 2092797Sktlim@umich.edu DPRINTFR(Config, "Unserializing '%s'\n", 2102797Sktlim@umich.edu obj->name()); 2112797Sktlim@umich.edu if(cp->sectionExists(obj->name())) 2122797Sktlim@umich.edu obj->unserialize(cp, obj->name()); 2132797Sktlim@umich.edu else 2142797Sktlim@umich.edu warn("Not unserializing '%s': no section found in checkpoint.\n", 2152797Sktlim@umich.edu obj->name()); 2162797Sktlim@umich.edu } 2172797Sktlim@umich.edu} 2182797Sktlim@umich.edu 2191031SN/A#ifdef DEBUG 2201031SN/A// 2211031SN/A// static function: flag which objects should have the debugger break 2221031SN/A// 2231031SN/Avoid 2241031SN/ASimObject::debugObjectBreak(const string &objs) 2251031SN/A{ 2261031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 2271031SN/A SimObjectList::const_iterator end = simObjectList.end(); 2281031SN/A 2291031SN/A ObjectMatch match(objs); 2301031SN/A for (; i != end; ++i) { 2311031SN/A SimObject *obj = *i; 2321031SN/A obj->doDebugBreak = match.match(obj->name()); 2331031SN/A } 2341031SN/A} 2351031SN/A 2361031SN/Avoid 2371031SN/AdebugObjectBreak(const char *objs) 2381031SN/A{ 2391031SN/A SimObject::debugObjectBreak(string(objs)); 2401031SN/A} 2411031SN/A#endif 2421031SN/A 243938SN/Avoid 244938SN/ASimObject::recordEvent(const std::string &stat) 245938SN/A{ 2464076Sbinkertn@umich.edu Stats::recordEvent(stat); 247938SN/A} 248938SN/A 2492901Ssaidi@eecs.umich.eduunsigned int 2502839Sktlim@umich.eduSimObject::drain(Event *drain_event) 2512797Sktlim@umich.edu{ 2522901Ssaidi@eecs.umich.edu state = Drained; 2532901Ssaidi@eecs.umich.edu return 0; 2542797Sktlim@umich.edu} 2552797Sktlim@umich.edu 2562609SN/Avoid 2572797Sktlim@umich.eduSimObject::resume() 2582609SN/A{ 2592901Ssaidi@eecs.umich.edu state = Running; 2602797Sktlim@umich.edu} 2612797Sktlim@umich.edu 2622797Sktlim@umich.eduvoid 2632797Sktlim@umich.eduSimObject::setMemoryMode(State new_mode) 2642797Sktlim@umich.edu{ 2652901Ssaidi@eecs.umich.edu panic("setMemoryMode() should only be called on systems"); 2662797Sktlim@umich.edu} 2672797Sktlim@umich.edu 2682797Sktlim@umich.eduvoid 2692797Sktlim@umich.eduSimObject::switchOut() 2702797Sktlim@umich.edu{ 2712797Sktlim@umich.edu panic("Unimplemented!"); 2722797Sktlim@umich.edu} 2732797Sktlim@umich.edu 2742797Sktlim@umich.eduvoid 2752797Sktlim@umich.eduSimObject::takeOverFrom(BaseCPU *cpu) 2762797Sktlim@umich.edu{ 2772797Sktlim@umich.edu panic("Unimplemented!"); 2782609SN/A} 279