pseudo_inst.hh revision 9659:403a4d20799a
12SN/A/* 21762SN/A * Copyright (c) 2012 ARM Limited 37778Sgblack@eecs.umich.edu * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307778Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336712Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3756SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386216Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396214Snate@binkert.org * 402SN/A * Authors: Nathan Binkert 411078SN/A */ 421114SN/A 431114SN/A#ifndef __SIM_PSEUDO_INST_HH__ 441114SN/A#define __SIM_PSEUDO_INST_HH__ 451114SN/A 461114SN/Aclass ThreadContext; 471114SN/A 481114SN/A//We need the "Tick" and "Addr" data types from here 491114SN/A#include "base/types.hh" 501114SN/A 511114SN/Anamespace PseudoInst { 521114SN/A 531114SN/A/** 541114SN/A * Execute a decoded M5 pseudo instruction 551114SN/A * 561114SN/A * The ISA-specific code is responsible to decode the pseudo inst 571114SN/A * function number and subfunction number. After that has been done, 581114SN/A * the rest of the instruction can be implemented in an ISA-agnostic 591114SN/A * manner using the ISA-specific getArguments functions. 601114SN/A * 611114SN/A * @param func M5 pseudo op major function number (see utility/m5/m5ops.h) 621114SN/A * @param subfunc M5 minor function number. Mainly used for annotations. 631114SN/A */ 641114SN/Auint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc); 651114SN/A 661114SN/Avoid arm(ThreadContext *tc); 671114SN/Avoid quiesce(ThreadContext *tc); 681114SN/Avoid quiesceSkip(ThreadContext *tc); 691114SN/Avoid quiesceNs(ThreadContext *tc, uint64_t ns); 701114SN/Avoid quiesceCycles(ThreadContext *tc, uint64_t cycles); 711114SN/Auint64_t quiesceTime(ThreadContext *tc); 721114SN/Auint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, 731114SN/A uint64_t offset); 741114SN/Auint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len, 751114SN/A uint64_t offset, Addr filenameAddr); 761114SN/Avoid loadsymbol(ThreadContext *xc); 771114SN/Avoid addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); 781114SN/Auint64_t initParam(ThreadContext *xc); 791114SN/Auint64_t rpns(ThreadContext *tc); 801114SN/Avoid wakeCPU(ThreadContext *tc, uint64_t cpuid); 811114SN/Avoid m5exit(ThreadContext *tc, Tick delay); 821114SN/Avoid m5fail(ThreadContext *tc, Tick delay, uint64_t code); 831114SN/Avoid resetstats(ThreadContext *tc, Tick delay, Tick period); 841114SN/Avoid dumpstats(ThreadContext *tc, Tick delay, Tick period); 851114SN/Avoid dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 861114SN/Avoid m5checkpoint(ThreadContext *tc, Tick delay, Tick period); 871114SN/Avoid debugbreak(ThreadContext *tc); 881114SN/Avoid switchcpu(ThreadContext *tc); 891114SN/Avoid workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid); 901114SN/Avoid workend(ThreadContext *tc, uint64_t workid, uint64_t threadid); 911114SN/A 921114SN/A} // namespace PseudoInst 931114SN/A 941114SN/A#endif // __SIM_PSEUDO_INST_HH__ 951114SN/A