pseudo_inst.hh revision 5504
1298SN/A/* 22188SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 3298SN/A * All rights reserved. 4298SN/A * 5298SN/A * Redistribution and use in source and binary forms, with or without 6298SN/A * modification, are permitted provided that the following conditions are 7298SN/A * met: redistributions of source code must retain the above copyright 8298SN/A * notice, this list of conditions and the following disclaimer; 9298SN/A * redistributions in binary form must reproduce the above copyright 10298SN/A * notice, this list of conditions and the following disclaimer in the 11298SN/A * documentation and/or other materials provided with the distribution; 12298SN/A * neither the name of the copyright holders nor the names of its 13298SN/A * contributors may be used to endorse or promote products derived from 14298SN/A * this software without specific prior written permission. 15298SN/A * 16298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19298SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20298SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21298SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22298SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23298SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24298SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25298SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26298SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 29298SN/A */ 30298SN/A 312680Sktlim@umich.educlass ThreadContext; 32298SN/A 332980Sgblack@eecs.umich.edu//We need the "Tick" and "Addr" data types from here 342081SN/A#include "sim/host.hh" 352081SN/A 365504Snate@binkert.orgnamespace PseudoInst { 37349SN/A 385504Snate@binkert.org/** 395504Snate@binkert.org * @todo these externs are only here for a hack in fullCPU::takeOver... 405504Snate@binkert.org */ 415504Snate@binkert.orgextern bool doStatisticsInsts; 425504Snate@binkert.orgextern bool doCheckpointInsts; 435504Snate@binkert.orgextern bool doQuiesce; 445504Snate@binkert.org 455504Snate@binkert.orgvoid arm(ThreadContext *tc); 465504Snate@binkert.orgvoid quiesce(ThreadContext *tc); 475504Snate@binkert.orgvoid quiesceNs(ThreadContext *tc, uint64_t ns); 485504Snate@binkert.orgvoid quiesceCycles(ThreadContext *tc, uint64_t cycles); 495504Snate@binkert.orguint64_t quiesceTime(ThreadContext *tc); 505504Snate@binkert.orgvoid m5exit(ThreadContext *tc, Tick delay); 515504Snate@binkert.orgvoid m5exit_old(ThreadContext *tc); 525504Snate@binkert.orgvoid loadsymbol(ThreadContext *xc); 535504Snate@binkert.orgvoid resetstats(ThreadContext *tc, Tick delay, Tick period); 545504Snate@binkert.orgvoid dumpstats(ThreadContext *tc, Tick delay, Tick period); 555504Snate@binkert.orgvoid dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 565504Snate@binkert.orgvoid m5checkpoint(ThreadContext *tc, Tick delay, Tick period); 575504Snate@binkert.orguint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, 585504Snate@binkert.org uint64_t offset); 595504Snate@binkert.orgvoid debugbreak(ThreadContext *tc); 605504Snate@binkert.orgvoid switchcpu(ThreadContext *tc); 615504Snate@binkert.orgvoid addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); 625504Snate@binkert.orgvoid anBegin(ThreadContext *tc, uint64_t cur); 635504Snate@binkert.orgvoid anWait(ThreadContext *tc, uint64_t cur, uint64_t wait); 645504Snate@binkert.org 655504Snate@binkert.org/* namespace PsuedoInst */ } 66