pseudo_inst.hh revision 2680
1298SN/A/* 22188SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 3298SN/A * All rights reserved. 4298SN/A * 5298SN/A * Redistribution and use in source and binary forms, with or without 6298SN/A * modification, are permitted provided that the following conditions are 7298SN/A * met: redistributions of source code must retain the above copyright 8298SN/A * notice, this list of conditions and the following disclaimer; 9298SN/A * redistributions in binary form must reproduce the above copyright 10298SN/A * notice, this list of conditions and the following disclaimer in the 11298SN/A * documentation and/or other materials provided with the distribution; 12298SN/A * neither the name of the copyright holders nor the names of its 13298SN/A * contributors may be used to endorse or promote products derived from 14298SN/A * this software without specific prior written permission. 15298SN/A * 16298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19298SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20298SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21298SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22298SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23298SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24298SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25298SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26298SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 29298SN/A */ 30298SN/A 312680Sktlim@umich.educlass ThreadContext; 32298SN/A 332081SN/A//We need the "Tick" data type from here 342081SN/A#include "sim/host.hh" 352081SN/A//We need the "Addr" data type from here 362081SN/A#include "arch/isa_traits.hh" 372081SN/A 38298SN/Anamespace AlphaPseudo 39298SN/A{ 40349SN/A /** 41349SN/A * @todo these externs are only here for a hack in fullCPU::takeOver... 42349SN/A */ 43349SN/A extern bool doStatisticsInsts; 44349SN/A extern bool doCheckpointInsts; 45349SN/A extern bool doQuiesce; 46349SN/A 472680Sktlim@umich.edu void arm(ThreadContext *tc); 482680Sktlim@umich.edu void quiesce(ThreadContext *tc); 492680Sktlim@umich.edu void quiesceNs(ThreadContext *tc, uint64_t ns); 502680Sktlim@umich.edu void quiesceCycles(ThreadContext *tc, uint64_t cycles); 512680Sktlim@umich.edu uint64_t quiesceTime(ThreadContext *tc); 522680Sktlim@umich.edu void ivlb(ThreadContext *tc); 532680Sktlim@umich.edu void ivle(ThreadContext *tc); 542680Sktlim@umich.edu void m5exit(ThreadContext *tc, Tick delay); 552680Sktlim@umich.edu void m5exit_old(ThreadContext *tc); 562680Sktlim@umich.edu void resetstats(ThreadContext *tc, Tick delay, Tick period); 572680Sktlim@umich.edu void dumpstats(ThreadContext *tc, Tick delay, Tick period); 582680Sktlim@umich.edu void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 592680Sktlim@umich.edu void m5checkpoint(ThreadContext *tc, Tick delay, Tick period); 602680Sktlim@umich.edu uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset); 612680Sktlim@umich.edu void debugbreak(ThreadContext *tc); 622680Sktlim@umich.edu void switchcpu(ThreadContext *tc); 632680Sktlim@umich.edu void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); 64298SN/A} 65