insttracer.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathan Binkert
42 */
43
44#ifndef __INSTRECORD_HH__
45#define __INSTRECORD_HH__
46
47#include "base/bigint.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"      // for InstSeqNum
51#include "cpu/static_inst.hh"
52#include "sim/sim_object.hh"
53
54class ThreadContext;
55
56namespace Trace {
57
58class InstRecord
59{
60  protected:
61    typedef TheISA::VectorReg VectorReg;
62
63    Tick when;
64
65    // The following fields are initialized by the constructor and
66    // thus guaranteed to be valid.
67    ThreadContext *thread;
68    // need to make this ref-counted so it doesn't go away before we
69    // dump the record
70    StaticInstPtr staticInst;
71    TheISA::PCState pc;
72    StaticInstPtr macroStaticInst;
73
74    // The remaining fields are only valid for particular instruction
75    // types (e.g, addresses for memory ops) or when particular
76    // options are enabled (e.g., tracing full register contents).
77    // Each data field has an associated valid flag to indicate
78    // whether the data field is valid.
79
80    /*** @defgroup mem
81     * @{
82     * Memory request information in the instruction accessed memory.
83     * @see mem_valid
84     */
85    Addr addr; ///< The address that was accessed
86    Addr size; ///< The size of the memory request
87    unsigned flags; ///< The flags that were assigned to the request.
88
89    /** @} */
90
91    /** @defgroup data
92     * If this instruction wrote any data values they're recorded here
93     * WARNING: Instructions are quite loose with with what they write
94     * since many instructions write multiple values (e.g. destintation
95     * register, flags, status, ...) This only captures the last write.
96     * @TODO fix this and record all destintations that an instruction writes
97     * @see data_status
98     */
99    union {
100        uint64_t as_int;
101        double as_double;
102        VectorReg as_vector;
103    } data;
104
105    /** @defgroup fetch_seq
106     * This records the serial number that the instruction was fetched in.
107     * @see fetch_seq_valid
108     */
109    InstSeqNum fetch_seq;
110
111    /** @defgroup commit_seq
112     * This records the instruction number that was committed in the pipeline
113     * @see cp_seq_valid
114     */
115    InstSeqNum cp_seq;
116
117    /** @ingroup data
118     * What size of data was written?
119     */
120    enum {
121        DataInvalid = 0,
122        DataInt8 = 1,   // set to equal number of bytes
123        DataInt16 = 2,
124        DataInt32 = 4,
125        DataInt64 = 8,
126        DataDouble = 3,
127        DataVector = sizeof(VectorReg),
128    } data_status;
129
130    /** @ingroup memory
131     * Are the memory fields in the record valid?
132     */
133    bool mem_valid;
134
135    /** @ingroup fetch_seq
136     * Are the fetch sequence number fields valid?
137     */
138    bool fetch_seq_valid;
139    /** @ingroup commit_seq
140     * Are the commit sequence number fields valid?
141     */
142    bool cp_seq_valid;
143
144    /** is the predicate for execution this inst true or false (not execed)?
145     */
146    bool predicate;
147
148  public:
149    InstRecord(Tick _when, ThreadContext *_thread,
150               const StaticInstPtr _staticInst,
151               TheISA::PCState _pc,
152               const StaticInstPtr _macroStaticInst = NULL)
153        : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
154        macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
155        fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
156        fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
157    { }
158
159    virtual ~InstRecord() { }
160
161    void setWhen(Tick new_when) { when = new_when; }
162    void setMem(Addr a, Addr s, unsigned f)
163    {
164        addr = a; size = s; flags = f; mem_valid = true;
165    }
166
167    void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
168    void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
169    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
170    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
171    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
172    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
173
174    void setData(int64_t d) { setData((uint64_t)d); }
175    void setData(int32_t d) { setData((uint32_t)d); }
176    void setData(int16_t d) { setData((uint16_t)d); }
177    void setData(int8_t d)  { setData((uint8_t)d); }
178
179    void setData(double d) { data.as_double = d; data_status = DataDouble; }
180    void setData(const VectorReg& v)
181    { data.as_vector = v; data_status = DataVector; }
182
183    void setFetchSeq(InstSeqNum seq)
184    { fetch_seq = seq; fetch_seq_valid = true; }
185
186    void setCPSeq(InstSeqNum seq)
187    { cp_seq = seq; cp_seq_valid = true; }
188
189    void setPredicate(bool val) { predicate = val; }
190
191    virtual void dump() = 0;
192
193  public:
194    Tick getWhen() const { return when; }
195    ThreadContext *getThread() const { return thread; }
196    StaticInstPtr getStaticInst() const { return staticInst; }
197    TheISA::PCState getPCState() const { return pc; }
198    StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
199
200    Addr getAddr() const { return addr; }
201    Addr getSize() const { return size; }
202    unsigned getFlags() const { return flags; }
203    bool getMemValid() const { return mem_valid; }
204
205    uint64_t getIntData() const { return data.as_int; }
206    double getFloatData() const { return data.as_double; }
207    const VectorReg &getVectorData() const { return data.as_vector; }
208    int getDataStatus() const { return data_status; }
209
210    InstSeqNum getFetchSeq() const { return fetch_seq; }
211    bool getFetchSeqValid() const { return fetch_seq_valid; }
212
213    InstSeqNum getCpSeq() const { return cp_seq; }
214    bool getCpSeqValid() const { return cp_seq_valid; }
215};
216
217class InstTracer : public SimObject
218{
219  public:
220    InstTracer(const Params *p) : SimObject(p)
221    {}
222
223    virtual ~InstTracer()
224    {};
225
226    virtual InstRecord *
227        getInstRecord(Tick when, ThreadContext *tc,
228                const StaticInstPtr staticInst, TheISA::PCState pc,
229                const StaticInstPtr macroStaticInst = NULL) = 0;
230};
231
232
233
234} // namespace Trace
235
236#endif // __INSTRECORD_HH__
237