insttracer.hh revision 4832
12568SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 38713Sandreas.hansson@arm.com * All rights reserved. 48713Sandreas.hansson@arm.com * 58713Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68713Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78713Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88713Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98713Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108713Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118713Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128713Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138713Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142568SN/A * this software without specific prior written permission. 152568SN/A * 162568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272568SN/A * 282568SN/A * Authors: Steve Reinhardt 292568SN/A * Nathan Binkert 302568SN/A */ 312568SN/A 322568SN/A#ifndef __INSTRECORD_HH__ 332568SN/A#define __INSTRECORD_HH__ 342568SN/A 352568SN/A#include "base/bigint.hh" 362568SN/A#include "base/trace.hh" 372568SN/A#include "cpu/inst_seq.hh" // for InstSeqNum 382568SN/A#include "cpu/static_inst.hh" 392665Ssaidi@eecs.umich.edu#include "sim/host.hh" 402665Ssaidi@eecs.umich.edu#include "sim/sim_object.hh" 412665Ssaidi@eecs.umich.edu 428713Sandreas.hansson@arm.comclass ThreadContext; 432568SN/A 442568SN/Anamespace Trace { 452568SN/A 462982Sstever@eecs.umich.educlass InstRecord 478713Sandreas.hansson@arm.com{ 488713Sandreas.hansson@arm.com protected: 492568SN/A Tick when; 502568SN/A 512568SN/A // The following fields are initialized by the constructor and 522568SN/A // thus guaranteed to be valid. 532568SN/A ThreadContext *thread; 542568SN/A // need to make this ref-counted so it doesn't go away before we 552568SN/A // dump the record 568229Snate@binkert.org StaticInstPtr staticInst; 572568SN/A Addr PC; 585386Sstever@gmail.com bool misspeculating; 596215Snate@binkert.org 602568SN/A // The remaining fields are only valid for particular instruction 612568SN/A // types (e.g, addresses for memory ops) or when particular 622568SN/A // options are enabled (e.g., tracing full register contents). 634762Snate@binkert.org // Each data field has an associated valid flag to indicate 642568SN/A // whether the data field is valid. 652568SN/A Addr addr; 668713Sandreas.hansson@arm.com bool addr_valid; 678713Sandreas.hansson@arm.com 688713Sandreas.hansson@arm.com union { 698713Sandreas.hansson@arm.com uint64_t as_int; 708713Sandreas.hansson@arm.com double as_double; 718713Sandreas.hansson@arm.com } data; 728713Sandreas.hansson@arm.com enum { 738713Sandreas.hansson@arm.com DataInvalid = 0, 748713Sandreas.hansson@arm.com DataInt8 = 1, // set to equal number of bytes 758713Sandreas.hansson@arm.com DataInt16 = 2, 768713Sandreas.hansson@arm.com DataInt32 = 4, 778713Sandreas.hansson@arm.com DataInt64 = 8, 788713Sandreas.hansson@arm.com DataDouble = 3 792568SN/A } data_status; 802568SN/A 812568SN/A InstSeqNum fetch_seq; 828713Sandreas.hansson@arm.com bool fetch_seq_valid; 838713Sandreas.hansson@arm.com 848713Sandreas.hansson@arm.com InstSeqNum cp_seq; 858713Sandreas.hansson@arm.com bool cp_seq_valid; 868713Sandreas.hansson@arm.com 878713Sandreas.hansson@arm.com public: 888713Sandreas.hansson@arm.com InstRecord(Tick _when, ThreadContext *_thread, 898713Sandreas.hansson@arm.com const StaticInstPtr &_staticInst, 908713Sandreas.hansson@arm.com Addr _pc, bool spec) 918713Sandreas.hansson@arm.com : when(_when), thread(_thread), 928713Sandreas.hansson@arm.com staticInst(_staticInst), PC(_pc), 938713Sandreas.hansson@arm.com misspeculating(spec) 948949Sandreas.hansson@arm.com { 958713Sandreas.hansson@arm.com data_status = DataInvalid; 968713Sandreas.hansson@arm.com addr_valid = false; 978713Sandreas.hansson@arm.com 988713Sandreas.hansson@arm.com fetch_seq_valid = false; 998713Sandreas.hansson@arm.com cp_seq_valid = false; 1008713Sandreas.hansson@arm.com } 1018713Sandreas.hansson@arm.com 1028713Sandreas.hansson@arm.com virtual ~InstRecord() { } 1038713Sandreas.hansson@arm.com 1048713Sandreas.hansson@arm.com void setAddr(Addr a) { addr = a; addr_valid = true; } 1058713Sandreas.hansson@arm.com 1068713Sandreas.hansson@arm.com void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 1078713Sandreas.hansson@arm.com void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } 1088713Sandreas.hansson@arm.com void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 1098713Sandreas.hansson@arm.com void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 1108713Sandreas.hansson@arm.com void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 1118713Sandreas.hansson@arm.com void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 1128713Sandreas.hansson@arm.com 1138713Sandreas.hansson@arm.com void setData(int64_t d) { setData((uint64_t)d); } 1148713Sandreas.hansson@arm.com void setData(int32_t d) { setData((uint32_t)d); } 1158713Sandreas.hansson@arm.com void setData(int16_t d) { setData((uint16_t)d); } 1168713Sandreas.hansson@arm.com void setData(int8_t d) { setData((uint8_t)d); } 1178713Sandreas.hansson@arm.com 1188713Sandreas.hansson@arm.com void setData(double d) { data.as_double = d; data_status = DataDouble; } 1198713Sandreas.hansson@arm.com 1208713Sandreas.hansson@arm.com void setFetchSeq(InstSeqNum seq) 1218713Sandreas.hansson@arm.com { fetch_seq = seq; fetch_seq_valid = true; } 1228713Sandreas.hansson@arm.com 1238713Sandreas.hansson@arm.com void setCPSeq(InstSeqNum seq) 1248713Sandreas.hansson@arm.com { cp_seq = seq; cp_seq_valid = true; } 1258922Swilliam.wang@arm.com 1262568SN/A virtual void dump() = 0; 1278713Sandreas.hansson@arm.com}; 1288713Sandreas.hansson@arm.com 1298713Sandreas.hansson@arm.comclass InstTracer : public SimObject 1302643Sstever@eecs.umich.edu{ 1312568SN/A public: 1322568SN/A InstTracer(const std::string & name) : SimObject(name) 1332643Sstever@eecs.umich.edu {} 1348851Sandreas.hansson@arm.com 1352643Sstever@eecs.umich.edu virtual ~InstTracer() 1362643Sstever@eecs.umich.edu {}; 1378851Sandreas.hansson@arm.com 1388713Sandreas.hansson@arm.com virtual InstRecord * 1398713Sandreas.hansson@arm.com getInstRecord(Tick when, ThreadContext *tc, 1408713Sandreas.hansson@arm.com const StaticInstPtr staticInst, Addr pc) = 0; 1418713Sandreas.hansson@arm.com}; 1428713Sandreas.hansson@arm.com 1438713Sandreas.hansson@arm.com 1448713Sandreas.hansson@arm.com 1458713Sandreas.hansson@arm.com}; // namespace Trace 1468713Sandreas.hansson@arm.com 1478713Sandreas.hansson@arm.com#endif // __INSTRECORD_HH__ 1488713Sandreas.hansson@arm.com