insttracer.hh revision 13610
114272Sgiacomo.travaglini@arm.com/* 212472Sglenn.bergmans@arm.com * Copyright (c) 2014, 2017 ARM Limited 312472Sglenn.bergmans@arm.com * All rights reserved 412472Sglenn.bergmans@arm.com * 512472Sglenn.bergmans@arm.com * The license below extends only to copyright in the software and shall 612472Sglenn.bergmans@arm.com * not be construed as granting a license to any other intellectual 712472Sglenn.bergmans@arm.com * property including but not limited to intellectual property relating 812472Sglenn.bergmans@arm.com * to a hardware implementation of the functionality of the software 912472Sglenn.bergmans@arm.com * licensed hereunder. You may use the software subject to the license 1012472Sglenn.bergmans@arm.com * terms below provided that you ensure that this notice is replicated 1112472Sglenn.bergmans@arm.com * unmodified and in its entirety in all distributions of the software, 1212472Sglenn.bergmans@arm.com * modified or unmodified, in source code or in binary form. 134486Sbinkertn@umich.edu * 144486Sbinkertn@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 154486Sbinkertn@umich.edu * All rights reserved. 164486Sbinkertn@umich.edu * 174486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu * this software without specific prior written permission. 274486Sbinkertn@umich.edu * 284486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu * 4012472Sglenn.bergmans@arm.com * Authors: Steve Reinhardt 414486Sbinkertn@umich.edu * Nathan Binkert 423102SN/A */ 433102SN/A 4412472Sglenn.bergmans@arm.com#ifndef __INSTRECORD_HH__ 4513665Sandreas.sandberg@arm.com#define __INSTRECORD_HH__ 4613892Sgabeblack@google.com 471310SN/A#include "arch/generic/vec_pred_reg.hh" 4813892Sgabeblack@google.com#include "arch/generic/vec_reg.hh" 491366SN/A#include "base/types.hh" 509338SAndreas.Sandberg@arm.com#include "cpu/inst_seq.hh" 511310SN/A#include "cpu/static_inst.hh" 528839Sandreas.hansson@arm.com#include "sim/sim_object.hh" 532542SN/A 541310SN/Aclass ThreadContext; 5512472Sglenn.bergmans@arm.com 5612472Sglenn.bergmans@arm.comnamespace Trace { 5712472Sglenn.bergmans@arm.com 5812472Sglenn.bergmans@arm.comclass InstRecord 5912472Sglenn.bergmans@arm.com{ 6012472Sglenn.bergmans@arm.com protected: 6112472Sglenn.bergmans@arm.com Tick when; 6212472Sglenn.bergmans@arm.com 6312472Sglenn.bergmans@arm.com // The following fields are initialized by the constructor and 6412472Sglenn.bergmans@arm.com // thus guaranteed to be valid. 6512472Sglenn.bergmans@arm.com ThreadContext *thread; 6612472Sglenn.bergmans@arm.com // need to make this ref-counted so it doesn't go away before we 6712472Sglenn.bergmans@arm.com // dump the record 6812472Sglenn.bergmans@arm.com StaticInstPtr staticInst; 6912472Sglenn.bergmans@arm.com TheISA::PCState pc; 7012472Sglenn.bergmans@arm.com StaticInstPtr macroStaticInst; 7112472Sglenn.bergmans@arm.com 7212472Sglenn.bergmans@arm.com // The remaining fields are only valid for particular instruction 7312472Sglenn.bergmans@arm.com // types (e.g, addresses for memory ops) or when particular 742542SN/A // options are enabled (e.g., tracing full register contents). 752542SN/A // Each data field has an associated valid flag to indicate 769338SAndreas.Sandberg@arm.com // whether the data field is valid. 771310SN/A 782542SN/A /*** @defgroup mem 799198Sandreas.hansson@arm.com * @{ 802565SN/A * Memory request information in the instruction accessed memory. 812565SN/A * @see mem_valid 822565SN/A */ 8311764Sandreas.sandberg@arm.com Addr addr; ///< The address that was accessed 842565SN/A Addr size; ///< The size of the memory request 858839Sandreas.hansson@arm.com unsigned flags; ///< The flags that were assigned to the request. 864439SN/A 8714272Sgiacomo.travaglini@arm.com /** @} */ 8814272Sgiacomo.travaglini@arm.com 8913930Sgiacomo.travaglini@arm.com /** @defgroup data 9013930Sgiacomo.travaglini@arm.com * If this instruction wrote any data values they're recorded here 9113930Sgiacomo.travaglini@arm.com * WARNING: Instructions are quite loose with with what they write 9213930Sgiacomo.travaglini@arm.com * since many instructions write multiple values (e.g. destintation 9313930Sgiacomo.travaglini@arm.com * register, flags, status, ...) This only captures the last write. 9413930Sgiacomo.travaglini@arm.com * @TODO fix this and record all destintations that an instruction writes 9513930Sgiacomo.travaglini@arm.com * @see data_status 9614272Sgiacomo.travaglini@arm.com */ 9714272Sgiacomo.travaglini@arm.com union { 9814272Sgiacomo.travaglini@arm.com uint64_t as_int; 9914272Sgiacomo.travaglini@arm.com double as_double; 10014272Sgiacomo.travaglini@arm.com ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec; 10114272Sgiacomo.travaglini@arm.com ::VecPredRegContainer<TheISA::VecPredRegSizeBits, 10214272Sgiacomo.travaglini@arm.com TheISA::VecPredRegHasPackedRepr>* as_pred; 10314272Sgiacomo.travaglini@arm.com } data; 10414272Sgiacomo.travaglini@arm.com 10514272Sgiacomo.travaglini@arm.com /** @defgroup fetch_seq 10614272Sgiacomo.travaglini@arm.com * This records the serial number that the instruction was fetched in. 1073812SN/A * @see fetch_seq_valid 1083812SN/A */ 1093812SN/A InstSeqNum fetch_seq; 11010127SAndreas.Bardsley@arm.com 1113812SN/A /** @defgroup commit_seq 1123814SN/A * This records the instruction number that was committed in the pipeline 1133814SN/A * @see cp_seq_valid 1143814SN/A */ 1153814SN/A InstSeqNum cp_seq; 1163812SN/A 1173814SN/A /** @ingroup data 1183814SN/A * What size of data was written? 1198461SAli.Saidi@ARM.com */ 1208461SAli.Saidi@ARM.com enum DataStatus { 1213812SN/A DataInvalid = 0, 1223812SN/A DataInt8 = 1, // set to equal number of bytes 1236122SSteve.Reinhardt@amd.com DataInt16 = 2, 1243812SN/A DataInt32 = 4, 1253812SN/A DataInt64 = 8, 1263812SN/A DataDouble = 3, 127 DataVec = 5, 128 DataVecPred = 6 129 } data_status; 130 131 /** @ingroup memory 132 * Are the memory fields in the record valid? 133 */ 134 bool mem_valid; 135 136 /** @ingroup fetch_seq 137 * Are the fetch sequence number fields valid? 138 */ 139 bool fetch_seq_valid; 140 /** @ingroup commit_seq 141 * Are the commit sequence number fields valid? 142 */ 143 bool cp_seq_valid; 144 145 /** is the predicate for execution this inst true or false (not execed)? 146 */ 147 bool predicate; 148 149 public: 150 InstRecord(Tick _when, ThreadContext *_thread, 151 const StaticInstPtr _staticInst, 152 TheISA::PCState _pc, 153 const StaticInstPtr _macroStaticInst = NULL) 154 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc), 155 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0), 156 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false), 157 fetch_seq_valid(false), cp_seq_valid(false), predicate(true) 158 { } 159 160 virtual ~InstRecord() 161 { 162 if (data_status == DataVec) { 163 assert(data.as_vec); 164 delete data.as_vec; 165 } else if (data_status == DataVecPred) { 166 assert(data.as_pred); 167 delete data.as_pred; 168 } 169 } 170 171 void setWhen(Tick new_when) { when = new_when; } 172 void setMem(Addr a, Addr s, unsigned f) 173 { 174 addr = a; size = s; flags = f; mem_valid = true; 175 } 176 177 template <typename T, size_t N> 178 void 179 setData(std::array<T, N> d) 180 { 181 data.as_int = d[0]; 182 data_status = (DataStatus)sizeof(T); 183 static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 || 184 sizeof(T) == DataInt32 || sizeof(T) == DataInt64, 185 "Type T has an unrecognized size."); 186 } 187 188 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 189 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 190 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 191 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 192 193 void setData(int64_t d) { setData((uint64_t)d); } 194 void setData(int32_t d) { setData((uint32_t)d); } 195 void setData(int16_t d) { setData((uint16_t)d); } 196 void setData(int8_t d) { setData((uint8_t)d); } 197 198 void setData(double d) { data.as_double = d; data_status = DataDouble; } 199 200 void 201 setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d) 202 { 203 data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d); 204 data_status = DataVec; 205 } 206 207 void 208 setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits, 209 TheISA::VecPredRegHasPackedRepr>& d) 210 { 211 data.as_pred = new ::VecPredRegContainer< 212 TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d); 213 data_status = DataVecPred; 214 } 215 216 void setFetchSeq(InstSeqNum seq) 217 { fetch_seq = seq; fetch_seq_valid = true; } 218 219 void setCPSeq(InstSeqNum seq) 220 { cp_seq = seq; cp_seq_valid = true; } 221 222 void setPredicate(bool val) { predicate = val; } 223 224 virtual void dump() = 0; 225 226 public: 227 Tick getWhen() const { return when; } 228 ThreadContext *getThread() const { return thread; } 229 StaticInstPtr getStaticInst() const { return staticInst; } 230 TheISA::PCState getPCState() const { return pc; } 231 StaticInstPtr getMacroStaticInst() const { return macroStaticInst; } 232 233 Addr getAddr() const { return addr; } 234 Addr getSize() const { return size; } 235 unsigned getFlags() const { return flags; } 236 bool getMemValid() const { return mem_valid; } 237 238 uint64_t getIntData() const { return data.as_int; } 239 double getFloatData() const { return data.as_double; } 240 int getDataStatus() const { return data_status; } 241 242 InstSeqNum getFetchSeq() const { return fetch_seq; } 243 bool getFetchSeqValid() const { return fetch_seq_valid; } 244 245 InstSeqNum getCpSeq() const { return cp_seq; } 246 bool getCpSeqValid() const { return cp_seq_valid; } 247}; 248 249class InstTracer : public SimObject 250{ 251 public: 252 InstTracer(const Params *p) : SimObject(p) 253 {} 254 255 virtual ~InstTracer() 256 {}; 257 258 virtual InstRecord * 259 getInstRecord(Tick when, ThreadContext *tc, 260 const StaticInstPtr staticInst, TheISA::PCState pc, 261 const StaticInstPtr macroStaticInst = NULL) = 0; 262}; 263 264 265 266} // namespace Trace 267 268#endif // __INSTRECORD_HH__ 269