dot_writer.py revision 9853
12689Sktlim@umich.edu# Copyright (c) 2012-2013 ARM Limited 22689Sktlim@umich.edu# All rights reserved. 32689Sktlim@umich.edu# 42689Sktlim@umich.edu# The license below extends only to copyright in the software and shall 52689Sktlim@umich.edu# not be construed as granting a license to any other intellectual 62689Sktlim@umich.edu# property including but not limited to intellectual property relating 72689Sktlim@umich.edu# to a hardware implementation of the functionality of the software 82689Sktlim@umich.edu# licensed hereunder. You may use the software subject to the license 92689Sktlim@umich.edu# terms below provided that you ensure that this notice is replicated 102689Sktlim@umich.edu# unmodified and in its entirety in all distributions of the software, 112689Sktlim@umich.edu# modified or unmodified, in source code or in binary form. 122689Sktlim@umich.edu# 132689Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 142689Sktlim@umich.edu# modification, are permitted provided that the following conditions are 152689Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 162689Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 172689Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 182689Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 192689Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 202689Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 212689Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 222689Sktlim@umich.edu# this software without specific prior written permission. 232689Sktlim@umich.edu# 242689Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252689Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262689Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272689Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282689Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292689Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302689Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312683Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 323402Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332683Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342683Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 353402Sktlim@umich.edu# 363402Sktlim@umich.edu# Authors: Andreas Hansson 372862Sktlim@umich.edu# Uri Wiener 382862Sktlim@umich.edu 392862Sktlim@umich.edu##################################################################### 403565Sgblack@eecs.umich.edu# 412862Sktlim@umich.edu# System visualization using DOT 423675Sktlim@umich.edu# 432862Sktlim@umich.edu# While config.ini and config.json provide an almost complete listing 442683Sktlim@umich.edu# of a system's components and connectivity, they lack a birds-eye 452683Sktlim@umich.edu# view. The output generated by do_dot() is a DOT-based figure (as a 463402Sktlim@umich.edu# pdf and an editable svg file) and its source dot code. Nodes are 473402Sktlim@umich.edu# components, and edges represent the memory hierarchy: the edges are 482683Sktlim@umich.edu# directed, from a master to slave. Initially all nodes are 495482Snate@binkert.org# generated, and then all edges are added. do_dot should be called 503280Sgblack@eecs.umich.edu# with the top-most SimObject (namely root but not necessarily), the 512683Sktlim@umich.edu# output folder and the output dot source filename. From the given 523402Sktlim@umich.edu# node, both processes (node and edge creation) is performed 533402Sktlim@umich.edu# recursivly, traversing all children of the given root. 543402Sktlim@umich.edu# 553402Sktlim@umich.edu# pydot is required. When missing, no output will be generated. 563280Sgblack@eecs.umich.edu# 572683Sktlim@umich.edu##################################################################### 582683Sktlim@umich.edu 592699Sktlim@umich.eduimport m5, os, re 602699Sktlim@umich.edufrom m5.SimObject import isRoot, isSimObjectVector 612683Sktlim@umich.edufrom m5.util import warn 622683Sktlim@umich.edutry: 633486Sktlim@umich.edu import pydot 643486Sktlim@umich.eduexcept: 653486Sktlim@umich.edu pydot = False 663486Sktlim@umich.edu 673486Sktlim@umich.edu# need to create all nodes (components) before creating edges (memory channels) 683486Sktlim@umich.edudef dot_create_nodes(simNode, callgraph): 693486Sktlim@umich.edu if isRoot(simNode): 703486Sktlim@umich.edu label = "root" 713486Sktlim@umich.edu else: 723486Sktlim@umich.edu label = simNode._name 732862Sktlim@umich.edu full_path = re.sub('\.', '_', simNode.path()) 742862Sktlim@umich.edu # add class name under the label 752862Sktlim@umich.edu label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 762862Sktlim@umich.edu 772862Sktlim@umich.edu # each component is a sub-graph (cluster) 782862Sktlim@umich.edu cluster = dot_create_cluster(simNode, full_path, label) 792862Sktlim@umich.edu 803442Sgblack@eecs.umich.edu # create nodes per port 813442Sgblack@eecs.umich.edu for port_name in simNode._ports.keys(): 822862Sktlim@umich.edu port = simNode._port_refs.get(port_name, None) 832862Sktlim@umich.edu if port != None: 842862Sktlim@umich.edu full_port_name = full_path + "_" + port_name 852862Sktlim@umich.edu port_node = dot_create_node(simNode, full_port_name, port_name) 862862Sktlim@umich.edu cluster.add_node(port_node) 872862Sktlim@umich.edu 882862Sktlim@umich.edu # recurse to children 892862Sktlim@umich.edu if simNode._children: 902862Sktlim@umich.edu for c in simNode._children: 912862Sktlim@umich.edu child = simNode._children[c] 922862Sktlim@umich.edu if isSimObjectVector(child): 932862Sktlim@umich.edu for obj in child: 942862Sktlim@umich.edu dot_create_nodes(obj, cluster) 952862Sktlim@umich.edu else: 962862Sktlim@umich.edu dot_create_nodes(child, cluster) 972862Sktlim@umich.edu 982862Sktlim@umich.edu callgraph.add_subgraph(cluster) 992862Sktlim@umich.edu 1002862Sktlim@umich.edu# create all edges according to memory hierarchy 1013442Sgblack@eecs.umich.edudef dot_create_edges(simNode, callgraph): 1023442Sgblack@eecs.umich.edu for port_name in simNode._ports.keys(): 1032862Sktlim@umich.edu port = simNode._port_refs.get(port_name, None) 1042862Sktlim@umich.edu if port != None: 1052862Sktlim@umich.edu full_path = re.sub('\.', '_', simNode.path()) 1062862Sktlim@umich.edu full_port_name = full_path + "_" + port_name 1072862Sktlim@umich.edu port_node = dot_create_node(simNode, full_port_name, port_name) 1082862Sktlim@umich.edu # create edges 1092862Sktlim@umich.edu if type(port) is m5.params.PortRef: 1102862Sktlim@umich.edu dot_add_edge(simNode, callgraph, full_port_name, port) 1112862Sktlim@umich.edu else: 1122862Sktlim@umich.edu for p in port.elements: 1132862Sktlim@umich.edu dot_add_edge(simNode, callgraph, full_port_name, p) 1142683Sktlim@umich.edu 1153675Sktlim@umich.edu # recurse to children 1163686Sktlim@umich.edu if simNode._children: 1173675Sktlim@umich.edu for c in simNode._children: 1183686Sktlim@umich.edu child = simNode._children[c] 1193686Sktlim@umich.edu if isSimObjectVector(child): 1203675Sktlim@umich.edu for obj in child: 1213675Sktlim@umich.edu dot_create_edges(obj, callgraph) 1223675Sktlim@umich.edu else: 1233686Sktlim@umich.edu dot_create_edges(child, callgraph) 1243675Sktlim@umich.edu 1253686Sktlim@umich.edudef dot_add_edge(simNode, callgraph, full_port_name, peerPort): 1263686Sktlim@umich.edu if peerPort.role == "MASTER": 1273686Sktlim@umich.edu peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 1284190Ssaidi@eecs.umich.edu + "." + peerPort.peer.name) 1294190Ssaidi@eecs.umich.edu callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 1304190Ssaidi@eecs.umich.edu 1314190Ssaidi@eecs.umich.edudef dot_create_cluster(simNode, full_path, label): 1323675Sktlim@umich.edu return pydot.Cluster( \ 1333675Sktlim@umich.edu full_path, \ 1343675Sktlim@umich.edu shape = "Mrecord", \ 1353675Sktlim@umich.edu label = label, \ 1363675Sktlim@umich.edu style = "\"rounded, filled\"", \ 1373686Sktlim@umich.edu color = "#000000", \ 1383675Sktlim@umich.edu fillcolor = dot_gen_colour(simNode), \ 1393686Sktlim@umich.edu fontname = "Arial", \ 1403686Sktlim@umich.edu fontsize = "14", \ 1413686Sktlim@umich.edu fontcolor = "#000000" \ 1424190Ssaidi@eecs.umich.edu ) 1434190Ssaidi@eecs.umich.edu 1444190Ssaidi@eecs.umich.edudef dot_create_node(simNode, full_path, label): 1454190Ssaidi@eecs.umich.edu return pydot.Node( \ 1463675Sktlim@umich.edu full_path, \ 1473675Sktlim@umich.edu shape = "Mrecord", \ 1483675Sktlim@umich.edu label = label, \ 1492683Sktlim@umich.edu style = "\"rounded, filled\"", \ 1502683Sktlim@umich.edu color = "#000000", \ 1512683Sktlim@umich.edu fillcolor = dot_gen_colour(simNode, True), \ 1522683Sktlim@umich.edu fontname = "Arial", \ 1532683Sktlim@umich.edu fontsize = "14", \ 1542683Sktlim@umich.edu fontcolor = "#000000" \ 1552683Sktlim@umich.edu ) 1562683Sktlim@umich.edu 1572683Sktlim@umich.edu# an enumerator for different kinds of node types, at the moment we 1582683Sktlim@umich.edu# discern the majority of node types, with the caches being the 1592683Sktlim@umich.edu# notable exception 1602683Sktlim@umich.educlass NodeType: 1612683Sktlim@umich.edu SYS = 0 1622683Sktlim@umich.edu CPU = 1 1632683Sktlim@umich.edu BUS = 2 1643402Sktlim@umich.edu MEM = 3 1653402Sktlim@umich.edu DEV = 4 1663402Sktlim@umich.edu OTHER = 5 1673402Sktlim@umich.edu 1683402Sktlim@umich.edu# based on the sim object, determine the node type 1693402Sktlim@umich.edudef get_node_type(simNode): 1703402Sktlim@umich.edu if isinstance(simNode, m5.objects.System): 1713402Sktlim@umich.edu return NodeType.SYS 1724434Ssaidi@eecs.umich.edu # NULL ISA has no BaseCPU or PioDevice, so check if these names 1734434Ssaidi@eecs.umich.edu # exists before using them 1743402Sktlim@umich.edu elif 'BaseCPU' in dir(m5.objects) and \ 1753675Sktlim@umich.edu isinstance(simNode, m5.objects.BaseCPU): 1763486Sktlim@umich.edu return NodeType.CPU 1773486Sktlim@umich.edu elif 'PioDevice' in dir(m5.objects) and \ 1783486Sktlim@umich.edu isinstance(simNode, m5.objects.PioDevice): 1793486Sktlim@umich.edu return NodeType.DEV 1803486Sktlim@umich.edu elif isinstance(simNode, m5.objects.BaseBus): 1813675Sktlim@umich.edu return NodeType.BUS 1823675Sktlim@umich.edu elif isinstance(simNode, m5.objects.AbstractMemory): 1833486Sktlim@umich.edu return NodeType.MEM 1843486Sktlim@umich.edu else: 1853486Sktlim@umich.edu return NodeType.OTHER 1863402Sktlim@umich.edu 1873402Sktlim@umich.edu# based on the node type, determine the colour as an RGB tuple, the 1883402Sktlim@umich.edu# palette is rather arbitrary at this point (some coherent natural 1893402Sktlim@umich.edu# tones), and someone that feels artistic should probably have a look 1903402Sktlim@umich.edudef get_type_colour(nodeType): 1913402Sktlim@umich.edu if nodeType == NodeType.SYS: 1923402Sktlim@umich.edu return (228, 231, 235) 1933402Sktlim@umich.edu elif nodeType == NodeType.CPU: 1943402Sktlim@umich.edu return (187, 198, 217) 1953675Sktlim@umich.edu elif nodeType == NodeType.BUS: 1963675Sktlim@umich.edu return (111, 121, 140) 1973402Sktlim@umich.edu elif nodeType == NodeType.MEM: 198 return (94, 89, 88) 199 elif nodeType == NodeType.DEV: 200 return (199, 167, 147) 201 elif nodeType == NodeType.OTHER: 202 # use a relatively gray shade 203 return (186, 182, 174) 204 205# generate colour for a node, either corresponding to a sim object or a 206# port 207def dot_gen_colour(simNode, isPort = False): 208 # determine the type of the current node, and also its parent, if 209 # the node is not the same type as the parent then we use the base 210 # colour for its type 211 node_type = get_node_type(simNode) 212 if simNode._parent: 213 parent_type = get_node_type(simNode._parent) 214 else: 215 parent_type = NodeType.OTHER 216 217 # if this node is the same type as the parent, then scale the 218 # colour based on the depth such that the deeper levels in the 219 # hierarchy get darker colours 220 if node_type == parent_type: 221 # start out with a depth of zero 222 depth = 0 223 parent = simNode._parent 224 # find the closes parent that is not the same type 225 while parent and get_node_type(parent) == parent_type: 226 depth = depth + 1 227 parent = parent._parent 228 node_colour = get_type_colour(parent_type) 229 # slightly arbitrary, but assume that the depth is less than 230 # five levels 231 r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour) 232 else: 233 node_colour = get_type_colour(node_type) 234 r, g, b = node_colour 235 236 # if we are colouring a port, then make it a slightly darker shade 237 # than the node that encapsulates it, once again use a magic constant 238 if isPort: 239 r, g, b = map(lambda x: 0.8 * x, (r, g, b)) 240 241 return dot_rgb_to_html(r, g, b) 242 243def dot_rgb_to_html(r, g, b): 244 return "#%.2x%.2x%.2x" % (r, g, b) 245 246def do_dot(root, outdir, dotFilename): 247 if not pydot: 248 return 249 # * use ranksep > 1.0 for for vertical separation between nodes 250 # especially useful if you need to annotate edges using e.g. visio 251 # which accepts svg format 252 # * no need for hoizontal separation as nothing moves horizonally 253 callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 254 dot_create_nodes(root, callgraph) 255 dot_create_edges(root, callgraph) 256 dot_filename = os.path.join(outdir, dotFilename) 257 callgraph.write(dot_filename) 258 try: 259 # dot crashes if the figure is extremely wide. 260 # So avoid terminating simulation unnecessarily 261 callgraph.write_svg(dot_filename + ".svg") 262 callgraph.write_pdf(dot_filename + ".pdf") 263 except: 264 warn("failed to generate dot output from %s", dot_filename) 265