dot_writer.py revision 13870:2536e3a4b58d
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Uri Wiener 38# Sascha Bischoff 39 40##################################################################### 41# 42# System visualization using DOT 43# 44# While config.ini and config.json provide an almost complete listing 45# of a system's components and connectivity, they lack a birds-eye 46# view. The output generated by do_dot() is a DOT-based figure (as a 47# pdf and an editable svg file) and its source dot code. Nodes are 48# components, and edges represent the memory hierarchy: the edges are 49# directed, from a master to slave. Initially all nodes are 50# generated, and then all edges are added. do_dot should be called 51# with the top-most SimObject (namely root but not necessarily), the 52# output folder and the output dot source filename. From the given 53# node, both processes (node and edge creation) is performed 54# recursivly, traversing all children of the given root. 55# 56# pydot is required. When missing, no output will be generated. 57# 58##################################################################### 59 60from __future__ import print_function 61from __future__ import absolute_import 62 63import m5, os, re 64from m5.SimObject import isRoot, isSimObjectVector 65from m5.params import PortRef, isNullPointer 66from m5.util import warn 67try: 68 import pydot 69except: 70 pydot = False 71 72def simnode_children(simNode): 73 for child in simNode._children.values(): 74 if isNullPointer(child): 75 continue 76 if isSimObjectVector(child): 77 for obj in child: 78 if not isNullPointer(obj): 79 yield obj 80 else: 81 yield child 82 83# need to create all nodes (components) before creating edges (memory channels) 84def dot_create_nodes(simNode, callgraph): 85 if isRoot(simNode): 86 label = "root" 87 else: 88 label = simNode._name 89 full_path = re.sub('\.', '_', simNode.path()) 90 # add class name under the label 91 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 92 93 # each component is a sub-graph (cluster) 94 cluster = dot_create_cluster(simNode, full_path, label) 95 96 # create nodes per port 97 for port_name in simNode._ports.keys(): 98 port = simNode._port_refs.get(port_name, None) 99 if port != None: 100 full_port_name = full_path + "_" + port_name 101 port_node = dot_create_node(simNode, full_port_name, port_name) 102 cluster.add_node(port_node) 103 104 # recurse to children 105 for child in simnode_children(simNode): 106 dot_create_nodes(child, cluster) 107 108 callgraph.add_subgraph(cluster) 109 110# create all edges according to memory hierarchy 111def dot_create_edges(simNode, callgraph): 112 for port_name in simNode._ports.keys(): 113 port = simNode._port_refs.get(port_name, None) 114 if port != None: 115 full_path = re.sub('\.', '_', simNode.path()) 116 full_port_name = full_path + "_" + port_name 117 port_node = dot_create_node(simNode, full_port_name, port_name) 118 # create edges 119 if isinstance(port, PortRef): 120 dot_add_edge(simNode, callgraph, full_port_name, port) 121 else: 122 for p in port.elements: 123 dot_add_edge(simNode, callgraph, full_port_name, p) 124 125 # recurse to children 126 for child in simnode_children(simNode): 127 dot_create_edges(child, callgraph) 128 129def dot_add_edge(simNode, callgraph, full_port_name, port): 130 peer = port.peer 131 full_peer_path = re.sub('\.', '_', peer.simobj.path()) 132 full_peer_port_name = full_peer_path + "_" + peer.name 133 134 # Each edge is encountered twice, once for each peer. We only want one 135 # edge, so we'll arbitrarily chose which peer "wins" based on their names. 136 if full_peer_port_name < full_port_name: 137 dir_type = { 138 (False, False) : 'both', 139 (True, False) : 'forward', 140 (False, True) : 'back', 141 (True, True) : 'none' 142 }[ (port.is_source, 143 peer.is_source) ] 144 edge = pydot.Edge(full_port_name, full_peer_port_name, dir=dir_type) 145 callgraph.add_edge(edge) 146 147def dot_create_cluster(simNode, full_path, label): 148 # get the parameter values of the node and use them as a tooltip 149 ini_strings = [] 150 for param in sorted(simNode._params.keys()): 151 value = simNode._values.get(param) 152 if value != None: 153 # parameter name = value in HTML friendly format 154 ini_strings.append(str(param) + "=" + 155 simNode._values[param].ini_str()) 156 # join all the parameters with an HTML newline 157 tooltip = " ".join(ini_strings) 158 159 return pydot.Cluster( \ 160 full_path, \ 161 shape = "Mrecord", \ 162 label = label, \ 163 tooltip = "\"" + tooltip + "\"", \ 164 style = "\"rounded, filled\"", \ 165 color = "#000000", \ 166 fillcolor = dot_gen_colour(simNode), \ 167 fontname = "Arial", \ 168 fontsize = "14", \ 169 fontcolor = "#000000" \ 170 ) 171 172def dot_create_node(simNode, full_path, label): 173 return pydot.Node( \ 174 full_path, \ 175 shape = "Mrecord", \ 176 label = label, \ 177 style = "\"rounded, filled\"", \ 178 color = "#000000", \ 179 fillcolor = dot_gen_colour(simNode, True), \ 180 fontname = "Arial", \ 181 fontsize = "14", \ 182 fontcolor = "#000000" \ 183 ) 184 185# an enumerator for different kinds of node types, at the moment we 186# discern the majority of node types, with the caches being the 187# notable exception 188class NodeType: 189 SYS = 0 190 CPU = 1 191 XBAR = 2 192 MEM = 3 193 DEV = 4 194 OTHER = 5 195 196# based on the sim object, determine the node type 197def get_node_type(simNode): 198 if isinstance(simNode, m5.objects.System): 199 return NodeType.SYS 200 # NULL ISA has no BaseCPU or PioDevice, so check if these names 201 # exists before using them 202 elif 'BaseCPU' in dir(m5.objects) and \ 203 isinstance(simNode, m5.objects.BaseCPU): 204 return NodeType.CPU 205 elif 'PioDevice' in dir(m5.objects) and \ 206 isinstance(simNode, m5.objects.PioDevice): 207 return NodeType.DEV 208 elif isinstance(simNode, m5.objects.BaseXBar): 209 return NodeType.XBAR 210 elif isinstance(simNode, m5.objects.AbstractMemory): 211 return NodeType.MEM 212 else: 213 return NodeType.OTHER 214 215# based on the node type, determine the colour as an RGB tuple, the 216# palette is rather arbitrary at this point (some coherent natural 217# tones), and someone that feels artistic should probably have a look 218def get_type_colour(nodeType): 219 if nodeType == NodeType.SYS: 220 return (228, 231, 235) 221 elif nodeType == NodeType.CPU: 222 return (187, 198, 217) 223 elif nodeType == NodeType.XBAR: 224 return (111, 121, 140) 225 elif nodeType == NodeType.MEM: 226 return (94, 89, 88) 227 elif nodeType == NodeType.DEV: 228 return (199, 167, 147) 229 elif nodeType == NodeType.OTHER: 230 # use a relatively gray shade 231 return (186, 182, 174) 232 233# generate colour for a node, either corresponding to a sim object or a 234# port 235def dot_gen_colour(simNode, isPort = False): 236 # determine the type of the current node, and also its parent, if 237 # the node is not the same type as the parent then we use the base 238 # colour for its type 239 node_type = get_node_type(simNode) 240 if simNode._parent: 241 parent_type = get_node_type(simNode._parent) 242 else: 243 parent_type = NodeType.OTHER 244 245 # if this node is the same type as the parent, then scale the 246 # colour based on the depth such that the deeper levels in the 247 # hierarchy get darker colours 248 if node_type == parent_type: 249 # start out with a depth of zero 250 depth = 0 251 parent = simNode._parent 252 # find the closes parent that is not the same type 253 while parent and get_node_type(parent) == parent_type: 254 depth = depth + 1 255 parent = parent._parent 256 node_colour = get_type_colour(parent_type) 257 # slightly arbitrary, but assume that the depth is less than 258 # five levels 259 r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour) 260 else: 261 node_colour = get_type_colour(node_type) 262 r, g, b = node_colour 263 264 # if we are colouring a port, then make it a slightly darker shade 265 # than the node that encapsulates it, once again use a magic constant 266 if isPort: 267 r, g, b = map(lambda x: 0.8 * x, (r, g, b)) 268 269 return dot_rgb_to_html(r, g, b) 270 271def dot_rgb_to_html(r, g, b): 272 return "#%.2x%.2x%.2x" % (r, g, b) 273 274# We need to create all of the clock domains. We abuse the alpha channel to get 275# the correct domain colouring. 276def dot_add_clk_domain(c_dom, v_dom): 277 label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\"" 278 label = re.sub('\.', '_', str(label)) 279 full_path = re.sub('\.', '_', str(c_dom)) 280 return pydot.Cluster( \ 281 full_path, \ 282 shape = "Mrecord", \ 283 label = label, \ 284 style = "\"rounded, filled, dashed\"", \ 285 color = "#000000", \ 286 fillcolor = "#AFC8AF8F", \ 287 fontname = "Arial", \ 288 fontsize = "14", \ 289 fontcolor = "#000000" \ 290 ) 291 292def dot_create_dvfs_nodes(simNode, callgraph, domain=None): 293 if isRoot(simNode): 294 label = "root" 295 else: 296 label = simNode._name 297 full_path = re.sub('\.', '_', simNode.path()) 298 # add class name under the label 299 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 300 301 # each component is a sub-graph (cluster) 302 cluster = dot_create_cluster(simNode, full_path, label) 303 304 # create nodes per port 305 for port_name in simNode._ports.keys(): 306 port = simNode._port_refs.get(port_name, None) 307 if port != None: 308 full_port_name = full_path + "_" + port_name 309 port_node = dot_create_node(simNode, full_port_name, port_name) 310 cluster.add_node(port_node) 311 312 # Dictionary of DVFS domains 313 dvfs_domains = {} 314 315 # recurse to children 316 for child in simnode_children(simNode): 317 try: 318 c_dom = child.__getattr__('clk_domain') 319 v_dom = c_dom.__getattr__('voltage_domain') 320 except AttributeError: 321 # Just re-use the domain from above 322 c_dom = domain 323 v_dom = c_dom.__getattr__('voltage_domain') 324 pass 325 326 if c_dom == domain or c_dom == None: 327 dot_create_dvfs_nodes(child, cluster, domain) 328 else: 329 if c_dom not in dvfs_domains: 330 dvfs_cluster = dot_add_clk_domain(c_dom, v_dom) 331 dvfs_domains[c_dom] = dvfs_cluster 332 else: 333 dvfs_cluster = dvfs_domains[c_dom] 334 dot_create_dvfs_nodes(child, dvfs_cluster, c_dom) 335 336 for key in dvfs_domains: 337 cluster.add_subgraph(dvfs_domains[key]) 338 339 callgraph.add_subgraph(cluster) 340 341def do_dot(root, outdir, dotFilename): 342 if not pydot: 343 return 344 # * use ranksep > 1.0 for for vertical separation between nodes 345 # especially useful if you need to annotate edges using e.g. visio 346 # which accepts svg format 347 # * no need for hoizontal separation as nothing moves horizonally 348 callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 349 dot_create_nodes(root, callgraph) 350 dot_create_edges(root, callgraph) 351 dot_filename = os.path.join(outdir, dotFilename) 352 callgraph.write(dot_filename) 353 try: 354 # dot crashes if the figure is extremely wide. 355 # So avoid terminating simulation unnecessarily 356 callgraph.write_svg(dot_filename + ".svg") 357 callgraph.write_pdf(dot_filename + ".pdf") 358 except: 359 warn("failed to generate dot output from %s", dot_filename) 360 361def do_dvfs_dot(root, outdir, dotFilename): 362 if not pydot: 363 return 364 365 # There is a chance that we are unable to resolve the clock or 366 # voltage domains. If so, we fail silently. 367 try: 368 dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 369 dot_create_dvfs_nodes(root, dvfsgraph) 370 dot_create_edges(root, dvfsgraph) 371 dot_filename = os.path.join(outdir, dotFilename) 372 dvfsgraph.write(dot_filename) 373 except: 374 warn("Failed to generate dot graph for DVFS domains") 375 return 376 377 try: 378 # dot crashes if the figure is extremely wide. 379 # So avoid terminating simulation unnecessarily 380 dvfsgraph.write_svg(dot_filename + ".svg") 381 dvfsgraph.write_pdf(dot_filename + ".pdf") 382 except: 383 warn("failed to generate dot output from %s", dot_filename) 384