xref: /gem5/src/proto/inst_dep_record.proto

// Copyright (c) 2013,2017 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Radhika Jagtap

syntax = "proto2";

// Put all the generated messages in a namespace
package ProtoMessage;

// Packet header for the o3cpu data dependency trace. The header fields are the
// identifier describing what object captured the trace, the version of this
// file format, the tick frequency of the object and the window size used to
// limit the register dependencies during capture.
message InstDepRecordHeader {
  required string obj_id = 1;
  optional uint32 ver = 2 [default = 0];
  required uint64 tick_freq = 3;
  required uint32 window_size = 4;
}

// Packet to encapsulate an instruction in the o3cpu data dependency trace.
// The required fields include the instruction sequence number and the type
// of the record associated with the instruction e.g. load. The request related
// fields are optional, namely address, size and flags. The dependency related
// information includes a repeated field for order dependencies and register
// dependencies for loads, stores and comp records. There is a field for the
// computational delay with respect to the dependency that completed last. A
// weight field is used to account for committed instruction that were
// filtered out before writing the trace and is used to estimate ROB
// occupancy during replay. An optional field is provided for the instruction
// PC.
message InstDepRecord {
  enum RecordType {
    INVALID = 0;
    LOAD = 1;
    STORE = 2;
    COMP = 3;
  }
  required uint64 seq_num = 1;
  required RecordType type = 2 [default = INVALID];
  optional uint64 p_addr = 3;
  optional uint32 size = 4;
  optional uint32 flags = 5;
  repeated uint64 rob_dep = 6;
  required uint64 comp_delay = 7;
  repeated uint64 reg_dep = 8;
  optional uint32 weight = 9;
  optional uint64 pc = 10;
  optional uint64 v_addr = 11;
  optional uint32 asid = 12;
}