1// Copyright (c) 2013,2017 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Radhika Jagtap 37 38syntax = "proto2"; 39 40// Put all the generated messages in a namespace 41package ProtoMessage; 42 43// Packet header for the o3cpu data dependency trace. The header fields are the 44// identifier describing what object captured the trace, the version of this 45// file format, the tick frequency of the object and the window size used to 46// limit the register dependencies during capture. 47message InstDepRecordHeader { 48 required string obj_id = 1; 49 optional uint32 ver = 2 [default = 0]; 50 required uint64 tick_freq = 3; 51 required uint32 window_size = 4; 52} 53 54// Packet to encapsulate an instruction in the o3cpu data dependency trace. 55// The required fields include the instruction sequence number and the type 56// of the record associated with the instruction e.g. load. The request related 57// fields are optional, namely address, size and flags. The dependency related 58// information includes a repeated field for order dependencies and register 59// dependencies for loads, stores and comp records. There is a field for the 60// computational delay with respect to the dependency that completed last. A 61// weight field is used to account for committed instruction that were 62// filtered out before writing the trace and is used to estimate ROB 63// occupancy during replay. An optional field is provided for the instruction 64// PC. 65message InstDepRecord { 66 enum RecordType { 67 INVALID = 0; 68 LOAD = 1; 69 STORE = 2; 70 COMP = 3; 71 } 72 required uint64 seq_num = 1; 73 required RecordType type = 2 [default = INVALID]; 74 optional uint64 p_addr = 3; 75 optional uint32 size = 4; 76 optional uint32 flags = 5; 77 repeated uint64 rob_dep = 6; 78 required uint64 comp_delay = 7; 79 repeated uint64 reg_dep = 8; 80 optional uint32 weight = 9; 81 optional uint64 pc = 10; 82 optional uint64 v_addr = 11; 83 optional uint32 asid = 12; 84}