inst.proto revision 11807:63325e5b0a9d
1// Copyright (c) 2014,2017 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Ali Saidi 37 38syntax = "proto2"; 39 40// Put all the generated messages in a namespace 41package ProtoMessage; 42 43// Packet header with the identifier describing what object captured 44// the trace, the version of this file format, and the tick frequency 45// for all the packet time stamps. 46message InstHeader { 47 required string obj_id = 1; 48 required uint32 ver = 2 [default = 0]; 49 required uint64 tick_freq = 3; 50 required bool has_mem = 4; 51} 52 53message Inst { 54 required uint64 pc = 1; 55 required fixed32 inst = 2; 56 optional uint32 nodeid = 3; 57 optional uint32 cpuid = 4; 58 optional fixed64 tick = 5; 59 60 enum InstType { 61 None = 0; 62 IntAlu = 1; 63 IntMul = 2; 64 IntDiv = 3; 65 FloatAdd = 4; 66 FloatCmp = 5; 67 FloatCvt = 6; 68 FloatMult = 7; 69 FloatDiv = 8; 70 FloatSqrt = 9; 71 SIMDIntAdd = 10; 72 SIMDIntAddAcc = 11; 73 SIMDIntAlu = 12; 74 SIMDIntCmp = 13; 75 SIMDIntCvt = 14; 76 SIMDMisc = 15; 77 SIMDIntMult = 16; 78 SIMDIntMultAcc = 17; 79 SIMDIntShift = 18; 80 SIMDIntShiftAcc = 19; 81 SIMDSqrt = 20; 82 SIMDFloatAdd = 21; 83 SIMDFloatAlu = 22; 84 SIMDFloatCmp = 23; 85 SIMDFloatCvt = 24; 86 SIMDFloatDiv = 25; 87 SIMDFloatMisc = 26; 88 SIMDFloatMult = 27; 89 SIMDFloatMultAdd = 28; 90 SIMDFloatSqrt = 29; 91 MemRead = 30; 92 MemWrite = 31; 93 IprAccess = 32; 94 InstPrefetch = 33; 95 } 96 97 optional InstType type = 6; // add, mul, fp add, load, store, simd add, … 98 optional uint32 inst_flags = 7; // execution mode information 99 100 // If the operation does one or more memory accesses 101 message MemAccess { 102 required uint64 addr = 1; 103 required uint32 size = 2; 104 optional uint32 mem_flags = 3; 105 } 106 repeated MemAccess mem_access = 8; 107} 108 109