simple_mem.hh revision 8931:7a1dfb191e3f 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic multi-ported memory with an infinite
58 * throughput and a fixed latency, potentially with a variance added
59 * to it. It uses a SimpleTimingPort to implement the timing accesses.
60 */
61class SimpleMemory : public AbstractMemory
62{
63
64  private:
65
66    class MemoryPort : public SimpleTimingPort
67    {
68        SimpleMemory& memory;
69
70      public:
71
72        MemoryPort(const std::string& _name, SimpleMemory& _memory);
73
74      protected:
75
76        virtual Tick recvAtomic(PacketPtr pkt);
77
78        virtual void recvFunctional(PacketPtr pkt);
79
80        virtual AddrRangeList getAddrRanges();
81
82    };
83
84    std::vector<MemoryPort*> ports;
85
86    Tick lat;
87    Tick lat_var;
88
89  public:
90
91    typedef SimpleMemoryParams Params;
92    SimpleMemory(const Params *p);
93    virtual ~SimpleMemory() { }
94
95    unsigned int drain(Event* de);
96
97    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
98    virtual void init();
99
100    const Params *
101    params() const
102    {
103        return dynamic_cast<const Params *>(_params);
104    }
105
106  protected:
107
108    Tick doAtomicAccess(PacketPtr pkt);
109    void doFunctionalAccess(PacketPtr pkt);
110    virtual Tick calculateLatency(PacketPtr pkt);
111
112};
113
114#endif //__SIMPLE_MEMORY_HH__
115