simple_mem.hh revision 4626
12155SN/A/* 22155SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32155SN/A * All rights reserved. 42155SN/A * 52155SN/A * Redistribution and use in source and binary forms, with or without 62155SN/A * modification, are permitted provided that the following conditions are 72155SN/A * met: redistributions of source code must retain the above copyright 82155SN/A * notice, this list of conditions and the following disclaimer; 92155SN/A * redistributions in binary form must reproduce the above copyright 102155SN/A * notice, this list of conditions and the following disclaimer in the 112155SN/A * documentation and/or other materials provided with the distribution; 122155SN/A * neither the name of the copyright holders nor the names of its 132155SN/A * contributors may be used to endorse or promote products derived from 142155SN/A * this software without specific prior written permission. 152155SN/A * 162155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272155SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu */ 302155SN/A 314202Sbinkertn@umich.edu/* @file 322155SN/A */ 337768SAli.Saidi@ARM.com 347768SAli.Saidi@ARM.com#ifndef __PHYSICAL_MEMORY_HH__ 357768SAli.Saidi@ARM.com#define __PHYSICAL_MEMORY_HH__ 362178SN/A 372178SN/A#include "base/range.hh" 382178SN/A#include "mem/mem_object.hh" 392178SN/A#include "mem/packet.hh" 402178SN/A#include "mem/tport.hh" 412178SN/A#include "sim/eventq.hh" 422178SN/A#include <map> 432178SN/A#include <string> 442178SN/A 452178SN/A// 462178SN/A// Functional model for a contiguous block of physical memory. (i.e. RAM) 472155SN/A// 485865Sksewell@umich.educlass PhysicalMemory : public MemObject 496181Sksewell@umich.edu{ 506181Sksewell@umich.edu class MemoryPort : public SimpleTimingPort 515865Sksewell@umich.edu { 523918Ssaidi@eecs.umich.edu PhysicalMemory *memory; 535865Sksewell@umich.edu 542623SN/A public: 553918Ssaidi@eecs.umich.edu 562155SN/A MemoryPort(const std::string &_name, PhysicalMemory *_memory); 572155SN/A 582292SN/A protected: 596181Sksewell@umich.edu 606181Sksewell@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 613918Ssaidi@eecs.umich.edu 622292SN/A virtual void recvFunctional(PacketPtr pkt); 632292SN/A 642292SN/A virtual void recvStatusChange(Status status); 653918Ssaidi@eecs.umich.edu 662292SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 672292SN/A bool &snoop); 682766Sktlim@umich.edu 692766Sktlim@umich.edu virtual int deviceBlockSize(); 702766Sktlim@umich.edu }; 712921Sktlim@umich.edu 722921Sktlim@umich.edu int numPorts; 732766Sktlim@umich.edu 742766Sktlim@umich.edu 755529Snate@binkert.org private: 762766Sktlim@umich.edu // prevent copying of a MainMemory object 774762Snate@binkert.org PhysicalMemory(const PhysicalMemory &specmem); 782155SN/A const PhysicalMemory &operator=(const PhysicalMemory &specmem); 792155SN/A 802155SN/A protected: 812155SN/A 822155SN/A class LockedAddr { 832155SN/A public: 842766Sktlim@umich.edu // on alpha, minimum LL/SC granularity is 16 bytes, so lower 852155SN/A // bits need to masked off. 865865Sksewell@umich.edu static const Addr Addr_Mask = 0xf; 872155SN/A 882155SN/A static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 892155SN/A 902155SN/A Addr addr; // locked address 912178SN/A int cpuNum; // locking CPU 922178SN/A int threadNum; // locking thread ID within CPU 937756SAli.Saidi@ARM.com 942766Sktlim@umich.edu // check for matching execution context 952178SN/A bool matchesContext(Request *req) 962178SN/A { 976994Snate@binkert.org return (cpuNum == req->getCpuNum() && 982178SN/A threadNum == req->getThreadNum()); 992766Sktlim@umich.edu } 1002766Sktlim@umich.edu 1012766Sktlim@umich.edu LockedAddr(Request *req) 1022788Sktlim@umich.edu : addr(mask(req->getPaddr())), 1032178SN/A cpuNum(req->getCpuNum()), 1042733Sktlim@umich.edu threadNum(req->getThreadNum()) 1052733Sktlim@umich.edu { 1062817Sksewell@umich.edu } 1072733Sktlim@umich.edu }; 1084486Sbinkertn@umich.edu 1094486Sbinkertn@umich.edu std::list<LockedAddr> lockedAddrList; 1104776Sgblack@eecs.umich.edu 1114776Sgblack@eecs.umich.edu // helper function for checkLockedAddrs(): we really want to 1128739Sgblack@eecs.umich.edu // inline a quick check for an empty locked addr list (hopefully 1136365Sgblack@eecs.umich.edu // the common case), and do the full list search (if necessary) in 1144486Sbinkertn@umich.edu // this out-of-line function 1154202Sbinkertn@umich.edu bool checkLockedAddrList(PacketPtr pkt); 1164202Sbinkertn@umich.edu 1174202Sbinkertn@umich.edu // Record the address of a load-locked operation so that we can 1188541Sgblack@eecs.umich.edu // clear the execution context's lock flag if a matching store is 1194202Sbinkertn@umich.edu // performed 1204202Sbinkertn@umich.edu void trackLoadLocked(PacketPtr pkt); 1214776Sgblack@eecs.umich.edu 1228739Sgblack@eecs.umich.edu // Compare a store address with any locked addresses so we can 1236365Sgblack@eecs.umich.edu // clear the lock flag appropriately. Return value set to 'false' 1244202Sbinkertn@umich.edu // if store operation should be suppressed (because it was a 1254202Sbinkertn@umich.edu // conditional store and the address was no longer locked by the 1264202Sbinkertn@umich.edu // requesting execution context), 'true' otherwise. Note that 1274202Sbinkertn@umich.edu // this method must be called on *all* stores since even 1285217Ssaidi@eecs.umich.edu // non-conditional stores must clear any matching lock addresses. 1294202Sbinkertn@umich.edu bool writeOK(PacketPtr pkt) { 1302155SN/A Request *req = pkt->req; 1314202Sbinkertn@umich.edu if (lockedAddrList.empty()) { 1324202Sbinkertn@umich.edu // no locked addrs: nothing to check, store_conditional fails 1332821Sktlim@umich.edu bool isLocked = pkt->isLocked(); 1344776Sgblack@eecs.umich.edu if (isLocked) { 1354776Sgblack@eecs.umich.edu req->setExtraData(0); 1364776Sgblack@eecs.umich.edu } 1374776Sgblack@eecs.umich.edu return !isLocked; // only do write if not an sc 1382766Sktlim@umich.edu } else { 1394202Sbinkertn@umich.edu // iterate over list... 1408335Snate@binkert.org return checkLockedAddrList(pkt); 1412733Sktlim@umich.edu } 1422733Sktlim@umich.edu } 1432733Sktlim@umich.edu 1442733Sktlim@umich.edu uint8_t *pmemAddr; 1452733Sktlim@umich.edu int pagePtr; 1462874Sktlim@umich.edu Tick lat; 1472874Sktlim@umich.edu std::vector<MemoryPort*> ports; 1482874Sktlim@umich.edu typedef std::vector<MemoryPort*>::iterator PortIterator; 1494202Sbinkertn@umich.edu 1502733Sktlim@umich.edu public: 1515192Ssaidi@eecs.umich.edu Addr new_page(); 1528335Snate@binkert.org uint64_t size() { return params()->addrRange.size(); } 1538335Snate@binkert.org uint64_t start() { return params()->addrRange.start; } 1548335Snate@binkert.org 1558335Snate@binkert.org struct Params 1568335Snate@binkert.org { 1578335Snate@binkert.org std::string name; 1588335Snate@binkert.org Range<Addr> addrRange; 1598335Snate@binkert.org Tick latency; 1608335Snate@binkert.org bool zero; 1618335Snate@binkert.org }; 1628335Snate@binkert.org 1638335Snate@binkert.org protected: 1648335Snate@binkert.org Params *_params; 1658335Snate@binkert.org 1668335Snate@binkert.org public: 1678335Snate@binkert.org const Params *params() const { return _params; } 1688335Snate@binkert.org PhysicalMemory(Params *p); 1698335Snate@binkert.org virtual ~PhysicalMemory(); 1708335Snate@binkert.org 1718335Snate@binkert.org public: 1728335Snate@binkert.org int deviceBlockSize(); 1738335Snate@binkert.org void getAddressRanges(AddrRangeList &resp, bool &snoop); 1748335Snate@binkert.org virtual Port *getPort(const std::string &if_name, int idx = -1); 1758335Snate@binkert.org void virtual init(); 1768471SGiacomo.Gabrielli@arm.com unsigned int drain(Event *de); 1778335Snate@binkert.org 1788335Snate@binkert.org protected: 1795192Ssaidi@eecs.umich.edu Tick doAtomicAccess(PacketPtr pkt); 1808232Snate@binkert.org void doFunctionalAccess(PacketPtr pkt); 1818232Snate@binkert.org virtual Tick calculateLatency(PacketPtr pkt); 1828232Snate@binkert.org void recvStatusChange(Port::Status status); 1838300Schander.sudanthi@arm.com 1848300Schander.sudanthi@arm.com public: 1855192Ssaidi@eecs.umich.edu virtual void serialize(std::ostream &os); 1868300Schander.sudanthi@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1878300Schander.sudanthi@arm.com 1886036Sksewell@umich.edu}; 1898300Schander.sudanthi@arm.com 1908300Schander.sudanthi@arm.com#endif //__PHYSICAL_MEMORY_HH__ 191