simple_mem.hh revision 10713
12391SN/A/* 29823Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38931Sandreas.hansson@arm.com * All rights reserved 48931Sandreas.hansson@arm.com * 58931Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68931Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78931Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88931Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98931Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108931Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118931Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128931Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138931Sandreas.hansson@arm.com * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 418931Sandreas.hansson@arm.com * Andreas Hansson 422391SN/A */ 432391SN/A 448931Sandreas.hansson@arm.com/** 458931Sandreas.hansson@arm.com * @file 468931Sandreas.hansson@arm.com * SimpleMemory declaration 472391SN/A */ 482391SN/A 498931Sandreas.hansson@arm.com#ifndef __SIMPLE_MEMORY_HH__ 508931Sandreas.hansson@arm.com#define __SIMPLE_MEMORY_HH__ 512391SN/A 529823Sandreas.hansson@arm.com#include <deque> 539823Sandreas.hansson@arm.com 548931Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 559823Sandreas.hansson@arm.com#include "mem/port.hh" 568931Sandreas.hansson@arm.com#include "params/SimpleMemory.hh" 574762SN/A 588931Sandreas.hansson@arm.com/** 599120Sandreas.hansson@arm.com * The simple memory is a basic single-ported memory controller with 609823Sandreas.hansson@arm.com * a configurable throughput and latency. 619823Sandreas.hansson@arm.com * 629264Sdjordje.kovacevic@arm.com * @sa \ref gem5MemorySystem "gem5 Memory System" 638931Sandreas.hansson@arm.com */ 648931Sandreas.hansson@arm.comclass SimpleMemory : public AbstractMemory 658931Sandreas.hansson@arm.com{ 662462SN/A 678931Sandreas.hansson@arm.com private: 686107SN/A 699823Sandreas.hansson@arm.com /** 709823Sandreas.hansson@arm.com * A deferred packet stores a packet along with its scheduled 719823Sandreas.hansson@arm.com * transmission time 729823Sandreas.hansson@arm.com */ 739823Sandreas.hansson@arm.com class DeferredPacket 749823Sandreas.hansson@arm.com { 759823Sandreas.hansson@arm.com 769823Sandreas.hansson@arm.com public: 779823Sandreas.hansson@arm.com 789823Sandreas.hansson@arm.com const Tick tick; 799823Sandreas.hansson@arm.com const PacketPtr pkt; 809823Sandreas.hansson@arm.com 819823Sandreas.hansson@arm.com DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 829823Sandreas.hansson@arm.com { } 839823Sandreas.hansson@arm.com }; 849823Sandreas.hansson@arm.com 859823Sandreas.hansson@arm.com class MemoryPort : public SlavePort 862413SN/A { 879228Sandreas.hansson@arm.com 889228Sandreas.hansson@arm.com private: 899228Sandreas.hansson@arm.com 908931Sandreas.hansson@arm.com SimpleMemory& memory; 912413SN/A 922413SN/A public: 932413SN/A 948931Sandreas.hansson@arm.com MemoryPort(const std::string& _name, SimpleMemory& _memory); 952413SN/A 962413SN/A protected: 972413SN/A 989228Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 992413SN/A 1009228Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 1012413SN/A 1029228Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 1039228Sandreas.hansson@arm.com 10410713Sandreas.hansson@arm.com void recvRespRetry(); 1059823Sandreas.hansson@arm.com 1069228Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 1072413SN/A 1082413SN/A }; 1092413SN/A 1109120Sandreas.hansson@arm.com MemoryPort port; 1112416SN/A 1129823Sandreas.hansson@arm.com /** 1139823Sandreas.hansson@arm.com * Latency from that a request is accepted until the response is 1149823Sandreas.hansson@arm.com * ready to be sent. 1159823Sandreas.hansson@arm.com */ 1169823Sandreas.hansson@arm.com const Tick latency; 1178719SN/A 1189823Sandreas.hansson@arm.com /** 1199823Sandreas.hansson@arm.com * Fudge factor added to the latency. 1209823Sandreas.hansson@arm.com */ 1219823Sandreas.hansson@arm.com const Tick latency_var; 1229823Sandreas.hansson@arm.com 1239823Sandreas.hansson@arm.com /** 1249823Sandreas.hansson@arm.com * Internal (unbounded) storage to mimic the delay caused by the 1259823Sandreas.hansson@arm.com * actual memory access. Note that this is where the packet spends 1269823Sandreas.hansson@arm.com * the memory latency. 1279823Sandreas.hansson@arm.com */ 1289823Sandreas.hansson@arm.com std::deque<DeferredPacket> packetQueue; 1299823Sandreas.hansson@arm.com 1309823Sandreas.hansson@arm.com /** 1319823Sandreas.hansson@arm.com * Bandwidth in ticks per byte. The regulation affects the 1329823Sandreas.hansson@arm.com * acceptance rate of requests and the queueing takes place after 1339823Sandreas.hansson@arm.com * the regulation. 1349823Sandreas.hansson@arm.com */ 1359228Sandreas.hansson@arm.com const double bandwidth; 1369228Sandreas.hansson@arm.com 1379228Sandreas.hansson@arm.com /** 1389228Sandreas.hansson@arm.com * Track the state of the memory as either idle or busy, no need 1399228Sandreas.hansson@arm.com * for an enum with only two states. 1409228Sandreas.hansson@arm.com */ 1419228Sandreas.hansson@arm.com bool isBusy; 1429228Sandreas.hansson@arm.com 1439228Sandreas.hansson@arm.com /** 1449228Sandreas.hansson@arm.com * Remember if we have to retry an outstanding request that 1459228Sandreas.hansson@arm.com * arrived while we were busy. 1469228Sandreas.hansson@arm.com */ 1479228Sandreas.hansson@arm.com bool retryReq; 1489228Sandreas.hansson@arm.com 1499228Sandreas.hansson@arm.com /** 1509823Sandreas.hansson@arm.com * Remember if we failed to send a response and are awaiting a 1519823Sandreas.hansson@arm.com * retry. This is only used as a check. 1529823Sandreas.hansson@arm.com */ 1539823Sandreas.hansson@arm.com bool retryResp; 1549823Sandreas.hansson@arm.com 1559823Sandreas.hansson@arm.com /** 1569228Sandreas.hansson@arm.com * Release the memory after being busy and send a retry if a 1579228Sandreas.hansson@arm.com * request was rejected in the meanwhile. 1589228Sandreas.hansson@arm.com */ 1599228Sandreas.hansson@arm.com void release(); 1609228Sandreas.hansson@arm.com 1619228Sandreas.hansson@arm.com EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent; 1629228Sandreas.hansson@arm.com 1639823Sandreas.hansson@arm.com /** 1649823Sandreas.hansson@arm.com * Dequeue a packet from our internal packet queue and move it to 1659823Sandreas.hansson@arm.com * the port where it will be sent as soon as possible. 1669823Sandreas.hansson@arm.com */ 1679823Sandreas.hansson@arm.com void dequeue(); 1689823Sandreas.hansson@arm.com 1699823Sandreas.hansson@arm.com EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent; 1709823Sandreas.hansson@arm.com 1719823Sandreas.hansson@arm.com /** 1729823Sandreas.hansson@arm.com * Detemine the latency. 1739823Sandreas.hansson@arm.com * 1749823Sandreas.hansson@arm.com * @return the latency seen by the current packet 1759823Sandreas.hansson@arm.com */ 1769823Sandreas.hansson@arm.com Tick getLatency() const; 1779823Sandreas.hansson@arm.com 1789349SAli.Saidi@ARM.com /** @todo this is a temporary workaround until the 4-phase code is 1799349SAli.Saidi@ARM.com * committed. upstream caches needs this packet until true is returned, so 1809349SAli.Saidi@ARM.com * hold onto it for deletion until a subsequent call 1819349SAli.Saidi@ARM.com */ 1829349SAli.Saidi@ARM.com std::vector<PacketPtr> pendingDelete; 1839349SAli.Saidi@ARM.com 1849823Sandreas.hansson@arm.com /** 1859823Sandreas.hansson@arm.com * If we need to drain, keep the drain manager around until we're 1869823Sandreas.hansson@arm.com * done here. 1879823Sandreas.hansson@arm.com */ 1889823Sandreas.hansson@arm.com DrainManager *drainManager; 1899823Sandreas.hansson@arm.com 1902391SN/A public: 1912391SN/A 1929228Sandreas.hansson@arm.com SimpleMemory(const SimpleMemoryParams *p); 1938931Sandreas.hansson@arm.com 1949342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 1958931Sandreas.hansson@arm.com 1969823Sandreas.hansson@arm.com BaseSlavePort& getSlavePort(const std::string& if_name, 1979823Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1989823Sandreas.hansson@arm.com void init(); 1992391SN/A 2008931Sandreas.hansson@arm.com protected: 2012391SN/A 2029823Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 2039823Sandreas.hansson@arm.com 2049823Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 2059823Sandreas.hansson@arm.com 2069228Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 2079823Sandreas.hansson@arm.com 20810713Sandreas.hansson@arm.com void recvRespRetry(); 2092391SN/A 2102391SN/A}; 2112391SN/A 2128931Sandreas.hansson@arm.com#endif //__SIMPLE_MEMORY_HH__ 213