RubyPort.cc revision 10917:c38f28fad4c3
111348Sandreas.sandberg@arm.com/* 211470Sandreas.sandberg@arm.com * Copyright (c) 2012-2013 ARM Limited 311348Sandreas.sandberg@arm.com * All rights reserved. 411348Sandreas.sandberg@arm.com * 511348Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 611348Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 711348Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 811348Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 911348Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1011348Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1111348Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1211348Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1311348Sandreas.sandberg@arm.com * 1411348Sandreas.sandberg@arm.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 1511348Sandreas.sandberg@arm.com * Copyright (c) 2011 Mark D. Hill and David A. Wood 1611348Sandreas.sandberg@arm.com * All rights reserved. 1711348Sandreas.sandberg@arm.com * 1811348Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1911348Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 2011348Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2111348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2211348Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2311348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2411348Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2511348Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2611348Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2711348Sandreas.sandberg@arm.com * this software without specific prior written permission. 2811348Sandreas.sandberg@arm.com * 2911348Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011348Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111348Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211348Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311348Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411348Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511348Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611348Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711348Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811348Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911348Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011348Sandreas.sandberg@arm.com */ 4111348Sandreas.sandberg@arm.com 4211348Sandreas.sandberg@arm.com#include "cpu/testers/rubytest/RubyTester.hh" 4311348Sandreas.sandberg@arm.com#include "debug/Config.hh" 4411348Sandreas.sandberg@arm.com#include "debug/Drain.hh" 4511348Sandreas.sandberg@arm.com#include "debug/Ruby.hh" 4611348Sandreas.sandberg@arm.com#include "mem/protocol/AccessPermission.hh" 4711348Sandreas.sandberg@arm.com#include "mem/ruby/slicc_interface/AbstractController.hh" 4811348Sandreas.sandberg@arm.com#include "mem/ruby/system/RubyPort.hh" 4911348Sandreas.sandberg@arm.com#include "mem/simple_mem.hh" 5011348Sandreas.sandberg@arm.com#include "sim/full_system.hh" 5111348Sandreas.sandberg@arm.com#include "sim/system.hh" 5211348Sandreas.sandberg@arm.com 5311348Sandreas.sandberg@arm.comRubyPort::RubyPort(const Params *p) 5411348Sandreas.sandberg@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 5511348Sandreas.sandberg@arm.com m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 5611348Sandreas.sandberg@arm.com system(p->system), 5711348Sandreas.sandberg@arm.com pioMasterPort(csprintf("%s.pio-master-port", name()), this), 5811348Sandreas.sandberg@arm.com pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 5911348Sandreas.sandberg@arm.com memMasterPort(csprintf("%s.mem-master-port", name()), this), 6011348Sandreas.sandberg@arm.com memSlavePort(csprintf("%s-mem-slave-port", name()), this, 6111348Sandreas.sandberg@arm.com p->ruby_system, p->ruby_system->getAccessBackingStore(), -1), 6211348Sandreas.sandberg@arm.com gotAddrRanges(p->port_master_connection_count) 6311348Sandreas.sandberg@arm.com{ 6411348Sandreas.sandberg@arm.com assert(m_version != -1); 6511348Sandreas.sandberg@arm.com 6611348Sandreas.sandberg@arm.com // create the slave ports based on the number of connected ports 6711348Sandreas.sandberg@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 6811348Sandreas.sandberg@arm.com slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 6911348Sandreas.sandberg@arm.com i), this, p->ruby_system, 7011348Sandreas.sandberg@arm.com p->ruby_system->getAccessBackingStore(), i)); 7111348Sandreas.sandberg@arm.com } 7211348Sandreas.sandberg@arm.com 7311348Sandreas.sandberg@arm.com // create the master ports based on the number of connected ports 7411348Sandreas.sandberg@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 7511348Sandreas.sandberg@arm.com master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 7611348Sandreas.sandberg@arm.com name(), i), this)); 7711348Sandreas.sandberg@arm.com } 7811348Sandreas.sandberg@arm.com} 7911348Sandreas.sandberg@arm.com 8011348Sandreas.sandberg@arm.comvoid 8111348Sandreas.sandberg@arm.comRubyPort::init() 8211348Sandreas.sandberg@arm.com{ 8311348Sandreas.sandberg@arm.com assert(m_controller != NULL); 8411348Sandreas.sandberg@arm.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 8511348Sandreas.sandberg@arm.com m_mandatory_q_ptr->setSender(this); 8611348Sandreas.sandberg@arm.com} 8711348Sandreas.sandberg@arm.com 8811348Sandreas.sandberg@arm.comBaseMasterPort & 8911348Sandreas.sandberg@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 9011348Sandreas.sandberg@arm.com{ 9111348Sandreas.sandberg@arm.com if (if_name == "mem_master_port") { 9211348Sandreas.sandberg@arm.com return memMasterPort; 9311348Sandreas.sandberg@arm.com } 9411348Sandreas.sandberg@arm.com 9511348Sandreas.sandberg@arm.com if (if_name == "pio_master_port") { 9611348Sandreas.sandberg@arm.com return pioMasterPort; 9711348Sandreas.sandberg@arm.com } 9811348Sandreas.sandberg@arm.com 9911348Sandreas.sandberg@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 10011348Sandreas.sandberg@arm.com // port 10111348Sandreas.sandberg@arm.com if (if_name != "master") { 10211348Sandreas.sandberg@arm.com // pass it along to our super class 10311348Sandreas.sandberg@arm.com return MemObject::getMasterPort(if_name, idx); 10411348Sandreas.sandberg@arm.com } else { 10511348Sandreas.sandberg@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 10611348Sandreas.sandberg@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 10711348Sandreas.sandberg@arm.com } 10811348Sandreas.sandberg@arm.com 10911470Sandreas.sandberg@arm.com return *master_ports[idx]; 11011348Sandreas.sandberg@arm.com } 11111348Sandreas.sandberg@arm.com} 11211348Sandreas.sandberg@arm.com 11311348Sandreas.sandberg@arm.comBaseSlavePort & 11411348Sandreas.sandberg@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 11511348Sandreas.sandberg@arm.com{ 11611348Sandreas.sandberg@arm.com if (if_name == "mem_slave_port") { 11711348Sandreas.sandberg@arm.com return memSlavePort; 11811348Sandreas.sandberg@arm.com } 11911348Sandreas.sandberg@arm.com 12011348Sandreas.sandberg@arm.com if (if_name == "pio_slave_port") 12111348Sandreas.sandberg@arm.com return pioSlavePort; 12211348Sandreas.sandberg@arm.com 12311348Sandreas.sandberg@arm.com // used by the CPUs to connect the caches to the interconnect, and 12411348Sandreas.sandberg@arm.com // for the x86 case also the interrupt master 12511348Sandreas.sandberg@arm.com if (if_name != "slave") { 12611348Sandreas.sandberg@arm.com // pass it along to our super class 12711348Sandreas.sandberg@arm.com return MemObject::getSlavePort(if_name, idx); 12811348Sandreas.sandberg@arm.com } else { 12911348Sandreas.sandberg@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 13011348Sandreas.sandberg@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 13111348Sandreas.sandberg@arm.com } 13211348Sandreas.sandberg@arm.com 13311348Sandreas.sandberg@arm.com return *slave_ports[idx]; 13411348Sandreas.sandberg@arm.com } 13511348Sandreas.sandberg@arm.com} 13611348Sandreas.sandberg@arm.com 13711348Sandreas.sandberg@arm.comRubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 13811348Sandreas.sandberg@arm.com RubyPort *_port) 13911348Sandreas.sandberg@arm.com : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 14011348Sandreas.sandberg@arm.com reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 14111348Sandreas.sandberg@arm.com{ 14211348Sandreas.sandberg@arm.com DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 14311348Sandreas.sandberg@arm.com} 144 145RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 146 RubyPort *_port) 147 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 148{ 149 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 150} 151 152RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 153 RubyPort *_port) 154 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 155 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 156{ 157 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 158} 159 160RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 161 RubySystem *_system, 162 bool _access_backing_store, PortID id) 163 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 164 ruby_system(_system), access_backing_store(_access_backing_store) 165{ 166 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 167} 168 169bool 170RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 171{ 172 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 173 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 174 175 // send next cycle 176 ruby_port->pioSlavePort.schedTimingResp( 177 pkt, curTick() + g_system_ptr->clockPeriod()); 178 return true; 179} 180 181bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 182{ 183 // got a response from a device 184 assert(pkt->isResponse()); 185 186 // First we must retrieve the request port from the sender State 187 RubyPort::SenderState *senderState = 188 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 189 MemSlavePort *port = senderState->port; 190 assert(port != NULL); 191 delete senderState; 192 193 // In FS mode, ruby memory will receive pio responses from devices 194 // and it must forward these responses back to the particular CPU. 195 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 196 pkt->getAddr(), port->name()); 197 198 // attempt to send the response in the next cycle 199 port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 200 201 return true; 202} 203 204bool 205RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 206{ 207 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 208 209 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 210 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 211 for (auto it = l.begin(); it != l.end(); ++it) { 212 if (it->contains(pkt->getAddr())) { 213 // generally it is not safe to assume success here as 214 // the port could be blocked 215 bool M5_VAR_USED success = 216 ruby_port->master_ports[i]->sendTimingReq(pkt); 217 assert(success); 218 return true; 219 } 220 } 221 } 222 panic("Should never reach here!\n"); 223} 224 225bool 226RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 227{ 228 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 229 pkt->getAddr(), id); 230 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 231 232 if (pkt->memInhibitAsserted()) 233 panic("RubyPort should never see an inhibited request\n"); 234 235 // Check for pio requests and directly send them to the dedicated 236 // pio port. 237 if (!isPhysMemAddress(pkt->getAddr())) { 238 assert(ruby_port->memMasterPort.isConnected()); 239 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 240 pkt->getAddr()); 241 242 // Save the port in the sender state object to be used later to 243 // route the response 244 pkt->pushSenderState(new SenderState(this)); 245 246 // send next cycle 247 ruby_port->memMasterPort.schedTimingReq(pkt, 248 curTick() + g_system_ptr->clockPeriod()); 249 return true; 250 } 251 252 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 253 RubySystem::getBlockSizeBytes()); 254 255 // Submit the ruby request 256 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 257 258 // If the request successfully issued then we should return true. 259 // Otherwise, we need to tell the port to retry at a later point 260 // and return false. 261 if (requestStatus == RequestStatus_Issued) { 262 // Save the port in the sender state object to be used later to 263 // route the response 264 pkt->pushSenderState(new SenderState(this)); 265 266 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 267 pkt->getAddr()); 268 return true; 269 } 270 271 // 272 // Unless one is using the ruby tester, record the stalled M5 port for 273 // later retry when the sequencer becomes free. 274 // 275 if (!ruby_port->m_usingRubyTester) { 276 ruby_port->addToRetryList(this); 277 } 278 279 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 280 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 281 282 return false; 283} 284 285void 286RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 287{ 288 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 289 290 // Check for pio requests and directly send them to the dedicated 291 // pio port. 292 if (!isPhysMemAddress(pkt->getAddr())) { 293 RubyPort *ruby_port M5_VAR_USED = static_cast<RubyPort *>(&owner); 294 assert(ruby_port->memMasterPort.isConnected()); 295 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 296 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 297 } 298 299 assert(pkt->getAddr() + pkt->getSize() <= 300 line_address(Address(pkt->getAddr())).getAddress() + 301 RubySystem::getBlockSizeBytes()); 302 303 if (access_backing_store) { 304 // The attached physmem contains the official version of data. 305 // The following command performs the real functional access. 306 // This line should be removed once Ruby supplies the official version 307 // of data. 308 ruby_system->getPhysMem()->functionalAccess(pkt); 309 } else { 310 bool accessSucceeded = false; 311 bool needsResponse = pkt->needsResponse(); 312 313 // Do the functional access on ruby memory 314 if (pkt->isRead()) { 315 accessSucceeded = ruby_system->functionalRead(pkt); 316 } else if (pkt->isWrite()) { 317 accessSucceeded = ruby_system->functionalWrite(pkt); 318 } else { 319 panic("Unsupported functional command %s\n", pkt->cmdString()); 320 } 321 322 // Unless the requester explicitly said otherwise, generate an error if 323 // the functional request failed 324 if (!accessSucceeded && !pkt->suppressFuncError()) { 325 fatal("Ruby functional %s failed for address %#x\n", 326 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 327 } 328 329 // turn packet around to go back to requester if response expected 330 if (needsResponse) { 331 pkt->setFunctionalResponseStatus(accessSucceeded); 332 } 333 334 DPRINTF(RubyPort, "Functional access %s!\n", 335 accessSucceeded ? "successful":"failed"); 336 } 337} 338 339void 340RubyPort::ruby_hit_callback(PacketPtr pkt) 341{ 342 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 343 pkt->getAddr()); 344 345 // The packet was destined for memory and has not yet been turned 346 // into a response 347 assert(system->isMemAddr(pkt->getAddr())); 348 assert(pkt->isRequest()); 349 350 // First we must retrieve the request port from the sender State 351 RubyPort::SenderState *senderState = 352 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 353 MemSlavePort *port = senderState->port; 354 assert(port != NULL); 355 delete senderState; 356 357 port->hitCallback(pkt); 358 359 // 360 // If we had to stall the MemSlavePorts, wake them up because the sequencer 361 // likely has free resources now. 362 // 363 if (!retryList.empty()) { 364 // 365 // Record the current list of ports to retry on a temporary list before 366 // calling sendRetry on those ports. sendRetry will cause an 367 // immediate retry, which may result in the ports being put back on the 368 // list. Therefore we want to clear the retryList before calling 369 // sendRetry. 370 // 371 std::vector<MemSlavePort *> curRetryList(retryList); 372 373 retryList.clear(); 374 375 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 376 DPRINTF(RubyPort, 377 "Sequencer may now be free. SendRetry to port %s\n", 378 (*i)->name()); 379 (*i)->sendRetryReq(); 380 } 381 } 382 383 testDrainComplete(); 384} 385 386void 387RubyPort::testDrainComplete() 388{ 389 //If we weren't able to drain before, we might be able to now. 390 if (drainState() == DrainState::Draining) { 391 unsigned int drainCount = outstandingCount(); 392 DPRINTF(Drain, "Drain count: %u\n", drainCount); 393 if (drainCount == 0) { 394 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 395 signalDrainDone(); 396 } 397 } 398} 399 400DrainState 401RubyPort::drain() 402{ 403 if (isDeadlockEventScheduled()) { 404 descheduleDeadlockEvent(); 405 } 406 407 // 408 // If the RubyPort is not empty, then it needs to clear all outstanding 409 // requests before it should call signalDrainDone() 410 // 411 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 412 if (outstandingCount() > 0) { 413 DPRINTF(Drain, "RubyPort not drained\n"); 414 return DrainState::Draining; 415 } else { 416 return DrainState::Drained; 417 } 418} 419 420void 421RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 422{ 423 bool needsResponse = pkt->needsResponse(); 424 425 // Unless specified at configuraiton, all responses except failed SC 426 // and Flush operations access M5 physical memory. 427 bool accessPhysMem = access_backing_store; 428 429 if (pkt->isLLSC()) { 430 if (pkt->isWrite()) { 431 if (pkt->req->getExtraData() != 0) { 432 // 433 // Successful SC packets convert to normal writes 434 // 435 pkt->convertScToWrite(); 436 } else { 437 // 438 // Failed SC packets don't access physical memory and thus 439 // the RubyPort itself must convert it to a response. 440 // 441 accessPhysMem = false; 442 } 443 } else { 444 // 445 // All LL packets convert to normal loads so that M5 PhysMem does 446 // not lock the blocks. 447 // 448 pkt->convertLlToRead(); 449 } 450 } 451 452 // Flush requests don't access physical memory 453 if (pkt->isFlush()) { 454 accessPhysMem = false; 455 } 456 457 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 458 459 if (accessPhysMem) { 460 ruby_system->getPhysMem()->access(pkt); 461 } else if (needsResponse) { 462 pkt->makeResponse(); 463 } 464 465 // turn packet around to go back to requester if response expected 466 if (needsResponse) { 467 DPRINTF(RubyPort, "Sending packet back over port\n"); 468 // send next cycle 469 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 470 } else { 471 delete pkt; 472 } 473 474 DPRINTF(RubyPort, "Hit callback done!\n"); 475} 476 477AddrRangeList 478RubyPort::PioSlavePort::getAddrRanges() const 479{ 480 // at the moment the assumption is that the master does not care 481 AddrRangeList ranges; 482 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 483 484 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 485 ranges.splice(ranges.begin(), 486 ruby_port->master_ports[i]->getAddrRanges()); 487 } 488 for (const auto M5_VAR_USED &r : ranges) 489 DPRINTF(RubyPort, "%s\n", r.to_string()); 490 return ranges; 491} 492 493bool 494RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 495{ 496 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 497 return ruby_port->system->isMemAddr(addr); 498} 499 500void 501RubyPort::ruby_eviction_callback(const Address& address) 502{ 503 DPRINTF(RubyPort, "Sending invalidations.\n"); 504 // This request is deleted in the stack-allocated packet destructor 505 // when this function exits 506 // TODO: should this really be using funcMasterId? 507 RequestPtr req = 508 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 509 // Use a single packet to signal all snooping ports of the invalidation. 510 // This assumes that snooping ports do NOT modify the packet/request 511 Packet pkt(req, MemCmd::InvalidateReq); 512 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 513 // check if the connected master port is snooping 514 if ((*p)->isSnooping()) { 515 // send as a snoop request 516 (*p)->sendTimingSnoopReq(&pkt); 517 } 518 } 519} 520 521void 522RubyPort::PioMasterPort::recvRangeChange() 523{ 524 RubyPort &r = static_cast<RubyPort &>(owner); 525 r.gotAddrRanges--; 526 if (r.gotAddrRanges == 0 && FullSystem) { 527 r.pioSlavePort.sendRangeChange(); 528 } 529} 530