RubyPort.cc revision 10412
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "sim/full_system.hh" 50#include "sim/system.hh" 51 52RubyPort::RubyPort(const Params *p) 53 : MemObject(p), m_version(p->version), m_controller(NULL), 54 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 55 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 56 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 57 memMasterPort(csprintf("%s.mem-master-port", name()), this), 58 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 59 p->ruby_system, p->access_phys_mem, -1), 60 gotAddrRanges(p->port_master_connection_count), drainManager(NULL), 61 system(p->system), access_phys_mem(p->access_phys_mem) 62{ 63 assert(m_version != -1); 64 65 // create the slave ports based on the number of connected ports 66 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 67 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 68 i), this, p->ruby_system, access_phys_mem, i)); 69 } 70 71 // create the master ports based on the number of connected ports 72 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 73 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 74 name(), i), this)); 75 } 76} 77 78void 79RubyPort::init() 80{ 81 assert(m_controller != NULL); 82 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 83 m_mandatory_q_ptr->setSender(this); 84} 85 86BaseMasterPort & 87RubyPort::getMasterPort(const std::string &if_name, PortID idx) 88{ 89 if (if_name == "mem_master_port") { 90 return memMasterPort; 91 } 92 93 if (if_name == "pio_master_port") { 94 return pioMasterPort; 95 } 96 97 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 98 // port 99 if (if_name != "master") { 100 // pass it along to our super class 101 return MemObject::getMasterPort(if_name, idx); 102 } else { 103 if (idx >= static_cast<PortID>(master_ports.size())) { 104 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 105 } 106 107 return *master_ports[idx]; 108 } 109} 110 111BaseSlavePort & 112RubyPort::getSlavePort(const std::string &if_name, PortID idx) 113{ 114 if (if_name == "mem_slave_port") { 115 return memSlavePort; 116 } 117 118 if (if_name == "pio_slave_port") 119 return pioSlavePort; 120 121 // used by the CPUs to connect the caches to the interconnect, and 122 // for the x86 case also the interrupt master 123 if (if_name != "slave") { 124 // pass it along to our super class 125 return MemObject::getSlavePort(if_name, idx); 126 } else { 127 if (idx >= static_cast<PortID>(slave_ports.size())) { 128 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 129 } 130 131 return *slave_ports[idx]; 132 } 133} 134 135RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 136 RubyPort *_port) 137 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 138{ 139 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 140} 141 142RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 143 RubyPort *_port) 144 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 145{ 146 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 147} 148 149RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 150 RubyPort *_port) 151 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 152{ 153 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 154} 155 156RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 157 RubySystem *_system, bool _access_phys_mem, PortID id) 158 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 159 ruby_system(_system), access_phys_mem(_access_phys_mem) 160{ 161 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 162} 163 164bool 165RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 166{ 167 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 168 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 169 170 // send next cycle 171 ruby_port->pioSlavePort.schedTimingResp( 172 pkt, curTick() + g_system_ptr->clockPeriod()); 173 return true; 174} 175 176bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 177{ 178 // got a response from a device 179 assert(pkt->isResponse()); 180 181 // In FS mode, ruby memory will receive pio responses from devices 182 // and it must forward these responses back to the particular CPU. 183 DPRINTF(RubyPort, "Pio response for address %#x, going to %d\n", 184 pkt->getAddr(), pkt->getDest()); 185 186 // First we must retrieve the request port from the sender State 187 RubyPort::SenderState *senderState = 188 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 189 MemSlavePort *port = senderState->port; 190 assert(port != NULL); 191 delete senderState; 192 193 // attempt to send the response in the next cycle 194 port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 195 196 return true; 197} 198 199bool 200RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 201{ 202 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 203 204 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 205 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 206 for (auto it = l.begin(); it != l.end(); ++it) { 207 if (it->contains(pkt->getAddr())) { 208 // generally it is not safe to assume success here as 209 // the port could be blocked 210 bool M5_VAR_USED success = 211 ruby_port->master_ports[i]->sendTimingReq(pkt); 212 assert(success); 213 return true; 214 } 215 } 216 } 217 panic("Should never reach here!\n"); 218} 219 220bool 221RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 222{ 223 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 224 pkt->getAddr(), id); 225 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 226 227 if (pkt->memInhibitAsserted()) 228 panic("RubyPort should never see an inhibited request\n"); 229 230 // Check for pio requests and directly send them to the dedicated 231 // pio port. 232 if (!isPhysMemAddress(pkt->getAddr())) { 233 assert(ruby_port->memMasterPort.isConnected()); 234 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 235 pkt->getAddr()); 236 237 // Save the port in the sender state object to be used later to 238 // route the response 239 pkt->pushSenderState(new SenderState(this)); 240 241 // send next cycle 242 ruby_port->memMasterPort.schedTimingReq(pkt, 243 curTick() + g_system_ptr->clockPeriod()); 244 return true; 245 } 246 247 // Save the port id to be used later to route the response 248 pkt->setSrc(id); 249 250 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 251 RubySystem::getBlockSizeBytes()); 252 253 // Submit the ruby request 254 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 255 256 // If the request successfully issued then we should return true. 257 // Otherwise, we need to tell the port to retry at a later point 258 // and return false. 259 if (requestStatus == RequestStatus_Issued) { 260 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 261 pkt->getAddr()); 262 return true; 263 } 264 265 // 266 // Unless one is using the ruby tester, record the stalled M5 port for 267 // later retry when the sequencer becomes free. 268 // 269 if (!ruby_port->m_usingRubyTester) { 270 ruby_port->addToRetryList(this); 271 } 272 273 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 274 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 275 276 return false; 277} 278 279void 280RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 281{ 282 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 283 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 284 285 // Check for pio requests and directly send them to the dedicated 286 // pio port. 287 if (!isPhysMemAddress(pkt->getAddr())) { 288 assert(ruby_port->memMasterPort.isConnected()); 289 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 290 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 291 } 292 293 assert(pkt->getAddr() + pkt->getSize() <= 294 line_address(Address(pkt->getAddr())).getAddress() + 295 RubySystem::getBlockSizeBytes()); 296 297 bool accessSucceeded = false; 298 bool needsResponse = pkt->needsResponse(); 299 300 // Do the functional access on ruby memory 301 if (pkt->isRead()) { 302 accessSucceeded = ruby_system->functionalRead(pkt); 303 } else if (pkt->isWrite()) { 304 accessSucceeded = ruby_system->functionalWrite(pkt); 305 } else { 306 panic("Unsupported functional command %s\n", pkt->cmdString()); 307 } 308 309 // Unless the requester explicitly said otherwise, generate an error if 310 // the functional request failed 311 if (!accessSucceeded && !pkt->suppressFuncError()) { 312 fatal("Ruby functional %s failed for address %#x\n", 313 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 314 } 315 316 if (access_phys_mem) { 317 // The attached physmem contains the official version of data. 318 // The following command performs the real functional access. 319 // This line should be removed once Ruby supplies the official version 320 // of data. 321 ruby_port->system->getPhysMem().functionalAccess(pkt); 322 } 323 324 // turn packet around to go back to requester if response expected 325 if (needsResponse) { 326 pkt->setFunctionalResponseStatus(accessSucceeded); 327 328 // @todo There should not be a reverse call since the response is 329 // communicated through the packet pointer 330 // DPRINTF(RubyPort, "Sending packet back over port\n"); 331 // sendFunctional(pkt); 332 } 333 DPRINTF(RubyPort, "Functional access %s!\n", 334 accessSucceeded ? "successful":"failed"); 335} 336 337void 338RubyPort::ruby_hit_callback(PacketPtr pkt) 339{ 340 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 341 pkt->getAddr()); 342 343 // The packet was destined for memory and has not yet been turned 344 // into a response 345 assert(system->isMemAddr(pkt->getAddr())); 346 assert(pkt->isRequest()); 347 348 // As it has not yet been turned around, the source field tells us 349 // which port it came from. 350 assert(pkt->getSrc() < slave_ports.size()); 351 352 slave_ports[pkt->getSrc()]->hitCallback(pkt); 353 354 // 355 // If we had to stall the MemSlavePorts, wake them up because the sequencer 356 // likely has free resources now. 357 // 358 if (!retryList.empty()) { 359 // 360 // Record the current list of ports to retry on a temporary list before 361 // calling sendRetry on those ports. sendRetry will cause an 362 // immediate retry, which may result in the ports being put back on the 363 // list. Therefore we want to clear the retryList before calling 364 // sendRetry. 365 // 366 std::vector<MemSlavePort *> curRetryList(retryList); 367 368 retryList.clear(); 369 370 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 371 DPRINTF(RubyPort, 372 "Sequencer may now be free. SendRetry to port %s\n", 373 (*i)->name()); 374 (*i)->sendRetry(); 375 } 376 } 377 378 testDrainComplete(); 379} 380 381void 382RubyPort::testDrainComplete() 383{ 384 //If we weren't able to drain before, we might be able to now. 385 if (drainManager != NULL) { 386 unsigned int drainCount = outstandingCount(); 387 DPRINTF(Drain, "Drain count: %u\n", drainCount); 388 if (drainCount == 0) { 389 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 390 drainManager->signalDrainDone(); 391 // Clear the drain manager once we're done with it. 392 drainManager = NULL; 393 } 394 } 395} 396 397unsigned int 398RubyPort::getChildDrainCount(DrainManager *dm) 399{ 400 int count = 0; 401 402 if (memMasterPort.isConnected()) { 403 count += memMasterPort.drain(dm); 404 DPRINTF(Config, "count after pio check %d\n", count); 405 } 406 407 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 408 count += (*p)->drain(dm); 409 DPRINTF(Config, "count after slave port check %d\n", count); 410 } 411 412 for (std::vector<PioMasterPort *>::iterator p = master_ports.begin(); 413 p != master_ports.end(); ++p) { 414 count += (*p)->drain(dm); 415 DPRINTF(Config, "count after master port check %d\n", count); 416 } 417 418 DPRINTF(Config, "final count %d\n", count); 419 return count; 420} 421 422unsigned int 423RubyPort::drain(DrainManager *dm) 424{ 425 if (isDeadlockEventScheduled()) { 426 descheduleDeadlockEvent(); 427 } 428 429 // 430 // If the RubyPort is not empty, then it needs to clear all outstanding 431 // requests before it should call drainManager->signalDrainDone() 432 // 433 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 434 bool need_drain = outstandingCount() > 0; 435 436 // 437 // Also, get the number of child ports that will also need to clear 438 // their buffered requests before they call drainManager->signalDrainDone() 439 // 440 unsigned int child_drain_count = getChildDrainCount(dm); 441 442 // Set status 443 if (need_drain) { 444 drainManager = dm; 445 446 DPRINTF(Drain, "RubyPort not drained\n"); 447 setDrainState(Drainable::Draining); 448 return child_drain_count + 1; 449 } 450 451 drainManager = NULL; 452 setDrainState(Drainable::Drained); 453 return child_drain_count; 454} 455 456void 457RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 458{ 459 bool needsResponse = pkt->needsResponse(); 460 461 // 462 // Unless specified at configuraiton, all responses except failed SC 463 // and Flush operations access M5 physical memory. 464 // 465 bool accessPhysMem = access_phys_mem; 466 467 if (pkt->isLLSC()) { 468 if (pkt->isWrite()) { 469 if (pkt->req->getExtraData() != 0) { 470 // 471 // Successful SC packets convert to normal writes 472 // 473 pkt->convertScToWrite(); 474 } else { 475 // 476 // Failed SC packets don't access physical memory and thus 477 // the RubyPort itself must convert it to a response. 478 // 479 accessPhysMem = false; 480 } 481 } else { 482 // 483 // All LL packets convert to normal loads so that M5 PhysMem does 484 // not lock the blocks. 485 // 486 pkt->convertLlToRead(); 487 } 488 } 489 490 // 491 // Flush requests don't access physical memory 492 // 493 if (pkt->isFlush()) { 494 accessPhysMem = false; 495 } 496 497 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 498 499 if (accessPhysMem) { 500 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 501 ruby_port->system->getPhysMem().access(pkt); 502 } else if (needsResponse) { 503 pkt->makeResponse(); 504 } 505 506 // turn packet around to go back to requester if response expected 507 if (needsResponse) { 508 DPRINTF(RubyPort, "Sending packet back over port\n"); 509 // send next cycle 510 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 511 } else { 512 delete pkt; 513 } 514 DPRINTF(RubyPort, "Hit callback done!\n"); 515} 516 517AddrRangeList 518RubyPort::PioSlavePort::getAddrRanges() const 519{ 520 // at the moment the assumption is that the master does not care 521 AddrRangeList ranges; 522 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 523 524 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 525 ranges.splice(ranges.begin(), 526 ruby_port->master_ports[i]->getAddrRanges()); 527 } 528 for (AddrRangeConstIter r = ranges.begin(); r != ranges.end(); ++r) 529 DPRINTF(RubyPort, "%s\n", r->to_string()); 530 return ranges; 531} 532 533bool 534RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 535{ 536 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 537 return ruby_port->system->isMemAddr(addr); 538} 539 540void 541RubyPort::ruby_eviction_callback(const Address& address) 542{ 543 DPRINTF(RubyPort, "Sending invalidations.\n"); 544 // This request is deleted in the stack-allocated packet destructor 545 // when this function exits 546 // TODO: should this really be using funcMasterId? 547 RequestPtr req = 548 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 549 // Use a single packet to signal all snooping ports of the invalidation. 550 // This assumes that snooping ports do NOT modify the packet/request 551 Packet pkt(req, MemCmd::InvalidationReq); 552 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 553 // check if the connected master port is snooping 554 if ((*p)->isSnooping()) { 555 // send as a snoop request 556 (*p)->sendTimingSnoopReq(&pkt); 557 } 558 } 559} 560 561void 562RubyPort::PioMasterPort::recvRangeChange() 563{ 564 RubyPort &r = static_cast<RubyPort &>(owner); 565 r.gotAddrRanges--; 566 if (r.gotAddrRanges == 0 && FullSystem) { 567 r.pioSlavePort.sendRangeChange(); 568 } 569} 570