RubyPort.cc revision 9662
16876Ssteve.reinhardt@amd.com/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 498923Sandreas.hansson@arm.com#include "sim/system.hh" 506285Snate@binkert.org 516876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 528922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 538922Swilliam.wang@arm.com m_mandatory_q_ptr(NULL), 548922Swilliam.wang@arm.com pio_port(csprintf("%s-pio-port", name()), this), 558922Swilliam.wang@arm.com m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 569342SAndreas.Sandberg@arm.com drainManager(NULL), ruby_system(p->ruby_system), system(p->system), 578922Swilliam.wang@arm.com waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 586876Ssteve.reinhardt@amd.com{ 596876Ssteve.reinhardt@amd.com assert(m_version != -1); 606876Ssteve.reinhardt@amd.com 618922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 628922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 638922Swilliam.wang@arm.com slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 648922Swilliam.wang@arm.com this, ruby_system, access_phys_mem)); 658922Swilliam.wang@arm.com } 667039Snate@binkert.org 678922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 688922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 698922Swilliam.wang@arm.com master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 708922Swilliam.wang@arm.com this)); 718922Swilliam.wang@arm.com } 726876Ssteve.reinhardt@amd.com} 736876Ssteve.reinhardt@amd.com 747039Snate@binkert.orgvoid 757039Snate@binkert.orgRubyPort::init() 766882SBrad.Beckmann@amd.com{ 776882SBrad.Beckmann@amd.com assert(m_controller != NULL); 786882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 799508Snilay@cs.wisc.edu m_mandatory_q_ptr->setSender(this); 806882SBrad.Beckmann@amd.com} 816882SBrad.Beckmann@amd.com 829294Sandreas.hansson@arm.comBaseMasterPort & 839294Sandreas.hansson@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 846876Ssteve.reinhardt@amd.com{ 858922Swilliam.wang@arm.com if (if_name == "pio_port") { 868922Swilliam.wang@arm.com return pio_port; 878922Swilliam.wang@arm.com } 888922Swilliam.wang@arm.com 898839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 908839Sandreas.hansson@arm.com // port 918922Swilliam.wang@arm.com if (if_name != "master") { 928922Swilliam.wang@arm.com // pass it along to our super class 938922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 948922Swilliam.wang@arm.com } else { 959294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 968922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 978922Swilliam.wang@arm.com } 988839Sandreas.hansson@arm.com 998922Swilliam.wang@arm.com return *master_ports[idx]; 1008839Sandreas.hansson@arm.com } 1018922Swilliam.wang@arm.com} 1028839Sandreas.hansson@arm.com 1039294Sandreas.hansson@arm.comBaseSlavePort & 1049294Sandreas.hansson@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 1058922Swilliam.wang@arm.com{ 1068922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1078922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1088922Swilliam.wang@arm.com if (if_name != "slave") { 1098922Swilliam.wang@arm.com // pass it along to our super class 1108922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1118922Swilliam.wang@arm.com } else { 1129294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 1138922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1148922Swilliam.wang@arm.com } 1158922Swilliam.wang@arm.com 1168922Swilliam.wang@arm.com return *slave_ports[idx]; 1177039Snate@binkert.org } 1186876Ssteve.reinhardt@amd.com} 1196882SBrad.Beckmann@amd.com 1207039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1216882SBrad.Beckmann@amd.com RubyPort *_port) 1229557Sandreas.hansson@arm.com : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 1236882SBrad.Beckmann@amd.com{ 1248922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 1256882SBrad.Beckmann@amd.com} 1266882SBrad.Beckmann@amd.com 1278436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1288436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1298922Swilliam.wang@arm.com : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 1308914Sandreas.hansson@arm.com ruby_port(_port), ruby_system(_system), 1318914Sandreas.hansson@arm.com _onRetryList(false), access_phys_mem(_access_phys_mem) 1326882SBrad.Beckmann@amd.com{ 1338922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 1346882SBrad.Beckmann@amd.com} 1356882SBrad.Beckmann@amd.com 1366882SBrad.Beckmann@amd.comTick 1376882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1386882SBrad.Beckmann@amd.com{ 1396882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1406882SBrad.Beckmann@amd.com return 0; 1416882SBrad.Beckmann@amd.com} 1426882SBrad.Beckmann@amd.com 1436882SBrad.Beckmann@amd.com 1446882SBrad.Beckmann@amd.combool 1458975Sandreas.hansson@arm.comRubyPort::PioPort::recvTimingResp(PacketPtr pkt) 1466882SBrad.Beckmann@amd.com{ 1477039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1487039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1498161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1506882SBrad.Beckmann@amd.com 1516882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1527039Snate@binkert.org RubyPort::SenderState *senderState = 1539542Sandreas.hansson@arm.com safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 1546882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1556882SBrad.Beckmann@amd.com assert(port != NULL); 1566882SBrad.Beckmann@amd.com delete senderState; 1577039Snate@binkert.org 1588975Sandreas.hansson@arm.com port->sendTimingResp(pkt); 1597039Snate@binkert.org 1606882SBrad.Beckmann@amd.com return true; 1616882SBrad.Beckmann@amd.com} 1626882SBrad.Beckmann@amd.com 1636882SBrad.Beckmann@amd.combool 1648975Sandreas.hansson@arm.comRubyPort::M5Port::recvTimingReq(PacketPtr pkt) 1656882SBrad.Beckmann@amd.com{ 1668161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1677039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1686882SBrad.Beckmann@amd.com 1698975Sandreas.hansson@arm.com //dsm: based on SimpleTimingPort::recvTimingReq(pkt); 1706882SBrad.Beckmann@amd.com 1719662Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) 1729662Sandreas.hansson@arm.com panic("RubyPort should never see an inhibited request\n"); 1736882SBrad.Beckmann@amd.com 1746922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1756922SBrad.Beckmann@amd.com // route the response 1769542Sandreas.hansson@arm.com pkt->pushSenderState(new SenderState(this)); 1776922SBrad.Beckmann@amd.com 1786882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1796882SBrad.Beckmann@amd.com // pio port. 1806882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1818851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 1828161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1836922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1846922SBrad.Beckmann@amd.com pkt->getAddr()); 1856882SBrad.Beckmann@amd.com 1869163Sandreas.hansson@arm.com // send next cycle 1879206Snilay@cs.wisc.edu ruby_port->pio_port.schedTimingReq(pkt, 1889206Snilay@cs.wisc.edu curTick() + g_system_ptr->clockPeriod()); 1899163Sandreas.hansson@arm.com return true; 1906882SBrad.Beckmann@amd.com } 1916882SBrad.Beckmann@amd.com 1928615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 1938615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 1947906SBrad.Beckmann@amd.com 1956882SBrad.Beckmann@amd.com // Submit the ruby request 1968615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 1977023SBrad.Beckmann@amd.com 1987550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 1997023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2007023SBrad.Beckmann@amd.com // false. 2017550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2028161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2036922SBrad.Beckmann@amd.com return true; 2046882SBrad.Beckmann@amd.com } 2057023SBrad.Beckmann@amd.com 2067910SBrad.Beckmann@amd.com // 2077910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2087910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2097910SBrad.Beckmann@amd.com // 2107910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2117910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2127910SBrad.Beckmann@amd.com } 2137910SBrad.Beckmann@amd.com 2148161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2157906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2167039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2177039Snate@binkert.org 2186922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2199542Sandreas.hansson@arm.com pkt->senderState = senderState->predecessor; 2206922SBrad.Beckmann@amd.com delete senderState; 2216922SBrad.Beckmann@amd.com return false; 2226882SBrad.Beckmann@amd.com} 2236882SBrad.Beckmann@amd.com 2248436SBrad.Beckmann@amd.comvoid 2258436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 2268436SBrad.Beckmann@amd.com{ 2278436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 2288436SBrad.Beckmann@amd.com pkt->getAddr()); 2298436SBrad.Beckmann@amd.com 2308436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2318436SBrad.Beckmann@amd.com // pio port. 2328436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 2338851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 2348436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 2358436SBrad.Beckmann@amd.com pkt->getAddr()); 2368436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 2378436SBrad.Beckmann@amd.com } 2388436SBrad.Beckmann@amd.com 2398436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 2408436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 2418436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2428436SBrad.Beckmann@amd.com 2438436SBrad.Beckmann@amd.com bool accessSucceeded = false; 2448436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 2458436SBrad.Beckmann@amd.com 2468436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 2478436SBrad.Beckmann@amd.com if (pkt->isRead()) { 2489270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalRead(pkt); 2498436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2509270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalWrite(pkt); 2518436SBrad.Beckmann@amd.com } else { 2528436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 2538436SBrad.Beckmann@amd.com pkt->cmdString()); 2548436SBrad.Beckmann@amd.com } 2558436SBrad.Beckmann@amd.com 2568436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 2578436SBrad.Beckmann@amd.com // the functional request failed 2588436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 2598436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 2608436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 2618436SBrad.Beckmann@amd.com } 2628436SBrad.Beckmann@amd.com 2638436SBrad.Beckmann@amd.com if (access_phys_mem) { 2648436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 2658436SBrad.Beckmann@amd.com // The following command performs the real functional access. 2668436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 2678436SBrad.Beckmann@amd.com // of data. 2688931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().functionalAccess(pkt); 2698436SBrad.Beckmann@amd.com } 2708436SBrad.Beckmann@amd.com 2718436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 2728436SBrad.Beckmann@amd.com if (needsResponse) { 2738436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 2748706Sandreas.hansson@arm.com 2758706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 2768706Sandreas.hansson@arm.com // communicated through the packet pointer 2778706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 2788706Sandreas.hansson@arm.com // sendFunctional(pkt); 2798436SBrad.Beckmann@amd.com } 2808436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 2818436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 2828436SBrad.Beckmann@amd.com} 2838436SBrad.Beckmann@amd.com 2846882SBrad.Beckmann@amd.comvoid 2856922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 2866882SBrad.Beckmann@amd.com{ 2876922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 2887039Snate@binkert.org RubyPort::SenderState *senderState = 2896922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 2906922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 2916922SBrad.Beckmann@amd.com assert(port != NULL); 2927039Snate@binkert.org 2936922SBrad.Beckmann@amd.com // pop the sender state from the packet 2949542Sandreas.hansson@arm.com pkt->senderState = senderState->predecessor; 2956922SBrad.Beckmann@amd.com delete senderState; 2966882SBrad.Beckmann@amd.com 2976882SBrad.Beckmann@amd.com port->hitCallback(pkt); 2987910SBrad.Beckmann@amd.com 2997910SBrad.Beckmann@amd.com // 3007910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 3017910SBrad.Beckmann@amd.com // likely has free resources now. 3027910SBrad.Beckmann@amd.com // 3037910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 3048162SBrad.Beckmann@amd.com // 3058162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3068162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3078162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3088162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3098162SBrad.Beckmann@amd.com // sendRetry. 3108162SBrad.Beckmann@amd.com // 3118162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 3128162SBrad.Beckmann@amd.com 3138162SBrad.Beckmann@amd.com retryList.clear(); 3148162SBrad.Beckmann@amd.com waitingOnSequencer = false; 3158162SBrad.Beckmann@amd.com 3168162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 3178162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 3188162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3197910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3207910SBrad.Beckmann@amd.com (*i)->name()); 3218162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 3228162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3237910SBrad.Beckmann@amd.com } 3247910SBrad.Beckmann@amd.com } 3258688Snilay@cs.wisc.edu 3268688Snilay@cs.wisc.edu testDrainComplete(); 3278688Snilay@cs.wisc.edu} 3288688Snilay@cs.wisc.edu 3298688Snilay@cs.wisc.eduvoid 3308688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 3318688Snilay@cs.wisc.edu{ 3328688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 3339342SAndreas.Sandberg@arm.com if (drainManager != NULL) { 3349245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 3359152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 3368688Snilay@cs.wisc.edu if (drainCount == 0) { 3379342SAndreas.Sandberg@arm.com DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 3389342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 3399342SAndreas.Sandberg@arm.com // Clear the drain manager once we're done with it. 3409342SAndreas.Sandberg@arm.com drainManager = NULL; 3418688Snilay@cs.wisc.edu } 3428688Snilay@cs.wisc.edu } 3438688Snilay@cs.wisc.edu} 3448688Snilay@cs.wisc.edu 3458688Snilay@cs.wisc.eduunsigned int 3469342SAndreas.Sandberg@arm.comRubyPort::getChildDrainCount(DrainManager *dm) 3478688Snilay@cs.wisc.edu{ 3488688Snilay@cs.wisc.edu int count = 0; 3498688Snilay@cs.wisc.edu 3508851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 3519342SAndreas.Sandberg@arm.com count += pio_port.drain(dm); 3528688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 3538688Snilay@cs.wisc.edu } 3548688Snilay@cs.wisc.edu 3558922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 3569342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3578922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 3588922Swilliam.wang@arm.com } 3598922Swilliam.wang@arm.com 3608922Swilliam.wang@arm.com for (std::vector<PioPort*>::iterator p = master_ports.begin(); 3618922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 3629342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3638922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 3648688Snilay@cs.wisc.edu } 3658688Snilay@cs.wisc.edu 3668688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 3678688Snilay@cs.wisc.edu 3688688Snilay@cs.wisc.edu return count; 3698688Snilay@cs.wisc.edu} 3708688Snilay@cs.wisc.edu 3718688Snilay@cs.wisc.eduunsigned int 3729342SAndreas.Sandberg@arm.comRubyPort::drain(DrainManager *dm) 3738688Snilay@cs.wisc.edu{ 3748688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 3758688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 3768688Snilay@cs.wisc.edu } 3778688Snilay@cs.wisc.edu 3789245Shestness@cs.wisc.edu // 3799245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 3809342SAndreas.Sandberg@arm.com // requests before it should call drainManager->signalDrainDone() 3819245Shestness@cs.wisc.edu // 3829245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 3839245Shestness@cs.wisc.edu bool need_drain = outstandingCount() > 0; 3849245Shestness@cs.wisc.edu 3859245Shestness@cs.wisc.edu // 3869245Shestness@cs.wisc.edu // Also, get the number of child ports that will also need to clear 3879342SAndreas.Sandberg@arm.com // their buffered requests before they call drainManager->signalDrainDone() 3889245Shestness@cs.wisc.edu // 3899342SAndreas.Sandberg@arm.com unsigned int child_drain_count = getChildDrainCount(dm); 3908688Snilay@cs.wisc.edu 3918688Snilay@cs.wisc.edu // Set status 3929245Shestness@cs.wisc.edu if (need_drain) { 3939342SAndreas.Sandberg@arm.com drainManager = dm; 3948688Snilay@cs.wisc.edu 3959152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 3969342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 3979245Shestness@cs.wisc.edu return child_drain_count + 1; 3988688Snilay@cs.wisc.edu } 3998688Snilay@cs.wisc.edu 4009342SAndreas.Sandberg@arm.com drainManager = NULL; 4019342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 4029245Shestness@cs.wisc.edu return child_drain_count; 4036882SBrad.Beckmann@amd.com} 4046882SBrad.Beckmann@amd.com 4056882SBrad.Beckmann@amd.comvoid 4066882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 4076882SBrad.Beckmann@amd.com{ 4086882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4096882SBrad.Beckmann@amd.com 4107550SBrad.Beckmann@amd.com // 4117915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 4128184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 4137550SBrad.Beckmann@amd.com // 4147915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 4157550SBrad.Beckmann@amd.com 4167550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4177550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4187550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4197550SBrad.Beckmann@amd.com // 4207550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4217550SBrad.Beckmann@amd.com // 4227550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4237550SBrad.Beckmann@amd.com } else { 4247550SBrad.Beckmann@amd.com // 4257550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4267550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4277550SBrad.Beckmann@amd.com // 4287550SBrad.Beckmann@amd.com accessPhysMem = false; 4297550SBrad.Beckmann@amd.com } 4307550SBrad.Beckmann@amd.com } else { 4317550SBrad.Beckmann@amd.com // 4327550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4337550SBrad.Beckmann@amd.com // not lock the blocks. 4347550SBrad.Beckmann@amd.com // 4357550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4367550SBrad.Beckmann@amd.com } 4377550SBrad.Beckmann@amd.com } 4388184Ssomayeh@cs.wisc.edu 4398184Ssomayeh@cs.wisc.edu // 4408184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4418184Ssomayeh@cs.wisc.edu // 4428184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4438184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4448184Ssomayeh@cs.wisc.edu } 4458184Ssomayeh@cs.wisc.edu 4468161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4476882SBrad.Beckmann@amd.com 4487550SBrad.Beckmann@amd.com if (accessPhysMem) { 4498931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().access(pkt); 4508184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4517915SBrad.Beckmann@amd.com pkt->makeResponse(); 4527550SBrad.Beckmann@amd.com } 4536882SBrad.Beckmann@amd.com 4546882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4556882SBrad.Beckmann@amd.com if (needsResponse) { 4568161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4579163Sandreas.hansson@arm.com // send next cycle 4589206Snilay@cs.wisc.edu schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 4596882SBrad.Beckmann@amd.com } else { 4606882SBrad.Beckmann@amd.com delete pkt; 4616882SBrad.Beckmann@amd.com } 4628161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 4636882SBrad.Beckmann@amd.com} 4646882SBrad.Beckmann@amd.com 4658922Swilliam.wang@arm.comAddrRangeList 4669090Sandreas.hansson@arm.comRubyPort::M5Port::getAddrRanges() const 4678922Swilliam.wang@arm.com{ 4688922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 4698922Swilliam.wang@arm.com AddrRangeList ranges; 4708922Swilliam.wang@arm.com return ranges; 4718922Swilliam.wang@arm.com} 4728922Swilliam.wang@arm.com 4736882SBrad.Beckmann@amd.combool 4746882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 4756882SBrad.Beckmann@amd.com{ 4768931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 4776882SBrad.Beckmann@amd.com} 4787909Shestness@cs.utexas.edu 4797909Shestness@cs.utexas.eduunsigned 4807909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 4817909Shestness@cs.utexas.edu{ 4827909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 4837909Shestness@cs.utexas.edu} 4848717Snilay@cs.wisc.edu 4858717Snilay@cs.wisc.eduvoid 4868717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 4878717Snilay@cs.wisc.edu{ 4888717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 4899633Sjthestness@gmail.com // This request is deleted in the stack-allocated packet destructor 4909633Sjthestness@gmail.com // when this function exits 4919633Sjthestness@gmail.com // TODO: should this really be using funcMasterId? 4929633Sjthestness@gmail.com RequestPtr req = 4939633Sjthestness@gmail.com new Request(address.getAddress(), 0, 0, Request::funcMasterId); 4949633Sjthestness@gmail.com // Use a single packet to signal all snooping ports of the invalidation. 4959633Sjthestness@gmail.com // This assumes that snooping ports do NOT modify the packet/request 4969633Sjthestness@gmail.com Packet pkt(req, MemCmd::InvalidationReq); 4978922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 4989088Sandreas.hansson@arm.com // check if the connected master port is snooping 4999088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 5008948Sandreas.hansson@arm.com // send as a snoop request 5019633Sjthestness@gmail.com (*p)->sendTimingSnoopReq(&pkt); 5028922Swilliam.wang@arm.com } 5038717Snilay@cs.wisc.edu } 5048717Snilay@cs.wisc.edu} 505