RubyPort.cc revision 9508
16876Ssteve.reinhardt@amd.com/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 498923Sandreas.hansson@arm.com#include "sim/system.hh" 506285Snate@binkert.org 516876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 528922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 538922Swilliam.wang@arm.com m_mandatory_q_ptr(NULL), 548922Swilliam.wang@arm.com pio_port(csprintf("%s-pio-port", name()), this), 558922Swilliam.wang@arm.com m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 569342SAndreas.Sandberg@arm.com drainManager(NULL), ruby_system(p->ruby_system), system(p->system), 578922Swilliam.wang@arm.com waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 586876Ssteve.reinhardt@amd.com{ 596876Ssteve.reinhardt@amd.com assert(m_version != -1); 606876Ssteve.reinhardt@amd.com 618922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 628922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 638922Swilliam.wang@arm.com slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 648922Swilliam.wang@arm.com this, ruby_system, access_phys_mem)); 658922Swilliam.wang@arm.com } 667039Snate@binkert.org 678922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 688922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 698922Swilliam.wang@arm.com master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 708922Swilliam.wang@arm.com this)); 718922Swilliam.wang@arm.com } 726876Ssteve.reinhardt@amd.com} 736876Ssteve.reinhardt@amd.com 747039Snate@binkert.orgvoid 757039Snate@binkert.orgRubyPort::init() 766882SBrad.Beckmann@amd.com{ 776882SBrad.Beckmann@amd.com assert(m_controller != NULL); 786882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 799508Snilay@cs.wisc.edu m_mandatory_q_ptr->setSender(this); 806882SBrad.Beckmann@amd.com} 816882SBrad.Beckmann@amd.com 829294Sandreas.hansson@arm.comBaseMasterPort & 839294Sandreas.hansson@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 846876Ssteve.reinhardt@amd.com{ 858922Swilliam.wang@arm.com if (if_name == "pio_port") { 868922Swilliam.wang@arm.com return pio_port; 878922Swilliam.wang@arm.com } 888922Swilliam.wang@arm.com 898839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 908839Sandreas.hansson@arm.com // port 918922Swilliam.wang@arm.com if (if_name != "master") { 928922Swilliam.wang@arm.com // pass it along to our super class 938922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 948922Swilliam.wang@arm.com } else { 959294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 968922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 978922Swilliam.wang@arm.com } 988839Sandreas.hansson@arm.com 998922Swilliam.wang@arm.com return *master_ports[idx]; 1008839Sandreas.hansson@arm.com } 1018922Swilliam.wang@arm.com} 1028839Sandreas.hansson@arm.com 1039294Sandreas.hansson@arm.comBaseSlavePort & 1049294Sandreas.hansson@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 1058922Swilliam.wang@arm.com{ 1068922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1078922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1088922Swilliam.wang@arm.com if (if_name != "slave") { 1098922Swilliam.wang@arm.com // pass it along to our super class 1108922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1118922Swilliam.wang@arm.com } else { 1129294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 1138922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1148922Swilliam.wang@arm.com } 1158922Swilliam.wang@arm.com 1168922Swilliam.wang@arm.com return *slave_ports[idx]; 1177039Snate@binkert.org } 1186876Ssteve.reinhardt@amd.com} 1196882SBrad.Beckmann@amd.com 1207039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1216882SBrad.Beckmann@amd.com RubyPort *_port) 1228922Swilliam.wang@arm.com : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 1238922Swilliam.wang@arm.com ruby_port(_port) 1246882SBrad.Beckmann@amd.com{ 1258922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 1266882SBrad.Beckmann@amd.com} 1276882SBrad.Beckmann@amd.com 1288436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1298436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1308922Swilliam.wang@arm.com : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 1318914Sandreas.hansson@arm.com ruby_port(_port), ruby_system(_system), 1328914Sandreas.hansson@arm.com _onRetryList(false), access_phys_mem(_access_phys_mem) 1336882SBrad.Beckmann@amd.com{ 1348922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 1356882SBrad.Beckmann@amd.com} 1366882SBrad.Beckmann@amd.com 1376882SBrad.Beckmann@amd.comTick 1386882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1396882SBrad.Beckmann@amd.com{ 1406882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1416882SBrad.Beckmann@amd.com return 0; 1426882SBrad.Beckmann@amd.com} 1436882SBrad.Beckmann@amd.com 1446882SBrad.Beckmann@amd.com 1456882SBrad.Beckmann@amd.combool 1468975Sandreas.hansson@arm.comRubyPort::PioPort::recvTimingResp(PacketPtr pkt) 1476882SBrad.Beckmann@amd.com{ 1487039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1497039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1508161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1516882SBrad.Beckmann@amd.com 1526882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1537039Snate@binkert.org RubyPort::SenderState *senderState = 1546882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1556882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1566882SBrad.Beckmann@amd.com assert(port != NULL); 1577039Snate@binkert.org 1586882SBrad.Beckmann@amd.com // pop the sender state from the packet 1596882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1606882SBrad.Beckmann@amd.com delete senderState; 1617039Snate@binkert.org 1628975Sandreas.hansson@arm.com port->sendTimingResp(pkt); 1637039Snate@binkert.org 1646882SBrad.Beckmann@amd.com return true; 1656882SBrad.Beckmann@amd.com} 1666882SBrad.Beckmann@amd.com 1676882SBrad.Beckmann@amd.combool 1688975Sandreas.hansson@arm.comRubyPort::M5Port::recvTimingReq(PacketPtr pkt) 1696882SBrad.Beckmann@amd.com{ 1708161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1717039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1726882SBrad.Beckmann@amd.com 1738975Sandreas.hansson@arm.com //dsm: based on SimpleTimingPort::recvTimingReq(pkt); 1746882SBrad.Beckmann@amd.com 1757039Snate@binkert.org // The received packets should only be M5 requests, which should never 1767039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1777039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1786882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1796882SBrad.Beckmann@amd.com 1806882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1816882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1826882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1836882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1846882SBrad.Beckmann@amd.com delete pkt; 1856882SBrad.Beckmann@amd.com return true; 1866882SBrad.Beckmann@amd.com } 1876882SBrad.Beckmann@amd.com 1886922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1896922SBrad.Beckmann@amd.com // route the response 1906922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1916922SBrad.Beckmann@amd.com 1926882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1936882SBrad.Beckmann@amd.com // pio port. 1946882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1958851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 1968161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1976922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1986922SBrad.Beckmann@amd.com pkt->getAddr()); 1996882SBrad.Beckmann@amd.com 2009163Sandreas.hansson@arm.com // send next cycle 2019206Snilay@cs.wisc.edu ruby_port->pio_port.schedTimingReq(pkt, 2029206Snilay@cs.wisc.edu curTick() + g_system_ptr->clockPeriod()); 2039163Sandreas.hansson@arm.com return true; 2046882SBrad.Beckmann@amd.com } 2056882SBrad.Beckmann@amd.com 2068615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 2078615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2087906SBrad.Beckmann@amd.com 2096882SBrad.Beckmann@amd.com // Submit the ruby request 2108615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2117023SBrad.Beckmann@amd.com 2127550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2137023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2147023SBrad.Beckmann@amd.com // false. 2157550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2168161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2176922SBrad.Beckmann@amd.com return true; 2186882SBrad.Beckmann@amd.com } 2197023SBrad.Beckmann@amd.com 2207910SBrad.Beckmann@amd.com // 2217910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2227910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2237910SBrad.Beckmann@amd.com // 2247910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2257910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2267910SBrad.Beckmann@amd.com } 2277910SBrad.Beckmann@amd.com 2288161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2297906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2307039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2317039Snate@binkert.org 2326922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2336922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2346922SBrad.Beckmann@amd.com delete senderState; 2356922SBrad.Beckmann@amd.com return false; 2366882SBrad.Beckmann@amd.com} 2376882SBrad.Beckmann@amd.com 2388436SBrad.Beckmann@amd.comvoid 2398436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 2408436SBrad.Beckmann@amd.com{ 2418436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 2428436SBrad.Beckmann@amd.com pkt->getAddr()); 2438436SBrad.Beckmann@amd.com 2448436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2458436SBrad.Beckmann@amd.com // pio port. 2468436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 2478851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 2488436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 2498436SBrad.Beckmann@amd.com pkt->getAddr()); 2508436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 2518436SBrad.Beckmann@amd.com } 2528436SBrad.Beckmann@amd.com 2538436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 2548436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 2558436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2568436SBrad.Beckmann@amd.com 2578436SBrad.Beckmann@amd.com bool accessSucceeded = false; 2588436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 2598436SBrad.Beckmann@amd.com 2608436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 2618436SBrad.Beckmann@amd.com if (pkt->isRead()) { 2629270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalRead(pkt); 2638436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2649270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalWrite(pkt); 2658436SBrad.Beckmann@amd.com } else { 2668436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 2678436SBrad.Beckmann@amd.com pkt->cmdString()); 2688436SBrad.Beckmann@amd.com } 2698436SBrad.Beckmann@amd.com 2708436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 2718436SBrad.Beckmann@amd.com // the functional request failed 2728436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 2738436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 2748436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 2758436SBrad.Beckmann@amd.com } 2768436SBrad.Beckmann@amd.com 2778436SBrad.Beckmann@amd.com if (access_phys_mem) { 2788436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 2798436SBrad.Beckmann@amd.com // The following command performs the real functional access. 2808436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 2818436SBrad.Beckmann@amd.com // of data. 2828931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().functionalAccess(pkt); 2838436SBrad.Beckmann@amd.com } 2848436SBrad.Beckmann@amd.com 2858436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 2868436SBrad.Beckmann@amd.com if (needsResponse) { 2878436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 2888706Sandreas.hansson@arm.com 2898706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 2908706Sandreas.hansson@arm.com // communicated through the packet pointer 2918706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 2928706Sandreas.hansson@arm.com // sendFunctional(pkt); 2938436SBrad.Beckmann@amd.com } 2948436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 2958436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 2968436SBrad.Beckmann@amd.com} 2978436SBrad.Beckmann@amd.com 2986882SBrad.Beckmann@amd.comvoid 2996922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 3006882SBrad.Beckmann@amd.com{ 3016922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 3027039Snate@binkert.org RubyPort::SenderState *senderState = 3036922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 3046922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 3056922SBrad.Beckmann@amd.com assert(port != NULL); 3067039Snate@binkert.org 3076922SBrad.Beckmann@amd.com // pop the sender state from the packet 3086922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 3096922SBrad.Beckmann@amd.com delete senderState; 3106882SBrad.Beckmann@amd.com 3116882SBrad.Beckmann@amd.com port->hitCallback(pkt); 3127910SBrad.Beckmann@amd.com 3137910SBrad.Beckmann@amd.com // 3147910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 3157910SBrad.Beckmann@amd.com // likely has free resources now. 3167910SBrad.Beckmann@amd.com // 3177910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 3188162SBrad.Beckmann@amd.com // 3198162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3208162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3218162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3228162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3238162SBrad.Beckmann@amd.com // sendRetry. 3248162SBrad.Beckmann@amd.com // 3258162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 3268162SBrad.Beckmann@amd.com 3278162SBrad.Beckmann@amd.com retryList.clear(); 3288162SBrad.Beckmann@amd.com waitingOnSequencer = false; 3298162SBrad.Beckmann@amd.com 3308162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 3318162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 3328162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3337910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3347910SBrad.Beckmann@amd.com (*i)->name()); 3358162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 3368162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3377910SBrad.Beckmann@amd.com } 3387910SBrad.Beckmann@amd.com } 3398688Snilay@cs.wisc.edu 3408688Snilay@cs.wisc.edu testDrainComplete(); 3418688Snilay@cs.wisc.edu} 3428688Snilay@cs.wisc.edu 3438688Snilay@cs.wisc.eduvoid 3448688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 3458688Snilay@cs.wisc.edu{ 3468688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 3479342SAndreas.Sandberg@arm.com if (drainManager != NULL) { 3489245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 3499152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 3508688Snilay@cs.wisc.edu if (drainCount == 0) { 3519342SAndreas.Sandberg@arm.com DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 3529342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 3539342SAndreas.Sandberg@arm.com // Clear the drain manager once we're done with it. 3549342SAndreas.Sandberg@arm.com drainManager = NULL; 3558688Snilay@cs.wisc.edu } 3568688Snilay@cs.wisc.edu } 3578688Snilay@cs.wisc.edu} 3588688Snilay@cs.wisc.edu 3598688Snilay@cs.wisc.eduunsigned int 3609342SAndreas.Sandberg@arm.comRubyPort::getChildDrainCount(DrainManager *dm) 3618688Snilay@cs.wisc.edu{ 3628688Snilay@cs.wisc.edu int count = 0; 3638688Snilay@cs.wisc.edu 3648851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 3659342SAndreas.Sandberg@arm.com count += pio_port.drain(dm); 3668688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 3678688Snilay@cs.wisc.edu } 3688688Snilay@cs.wisc.edu 3698922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 3709342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3718922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 3728922Swilliam.wang@arm.com } 3738922Swilliam.wang@arm.com 3748922Swilliam.wang@arm.com for (std::vector<PioPort*>::iterator p = master_ports.begin(); 3758922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 3769342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3778922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 3788688Snilay@cs.wisc.edu } 3798688Snilay@cs.wisc.edu 3808688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 3818688Snilay@cs.wisc.edu 3828688Snilay@cs.wisc.edu return count; 3838688Snilay@cs.wisc.edu} 3848688Snilay@cs.wisc.edu 3858688Snilay@cs.wisc.eduunsigned int 3869342SAndreas.Sandberg@arm.comRubyPort::drain(DrainManager *dm) 3878688Snilay@cs.wisc.edu{ 3888688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 3898688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 3908688Snilay@cs.wisc.edu } 3918688Snilay@cs.wisc.edu 3929245Shestness@cs.wisc.edu // 3939245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 3949342SAndreas.Sandberg@arm.com // requests before it should call drainManager->signalDrainDone() 3959245Shestness@cs.wisc.edu // 3969245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 3979245Shestness@cs.wisc.edu bool need_drain = outstandingCount() > 0; 3989245Shestness@cs.wisc.edu 3999245Shestness@cs.wisc.edu // 4009245Shestness@cs.wisc.edu // Also, get the number of child ports that will also need to clear 4019342SAndreas.Sandberg@arm.com // their buffered requests before they call drainManager->signalDrainDone() 4029245Shestness@cs.wisc.edu // 4039342SAndreas.Sandberg@arm.com unsigned int child_drain_count = getChildDrainCount(dm); 4048688Snilay@cs.wisc.edu 4058688Snilay@cs.wisc.edu // Set status 4069245Shestness@cs.wisc.edu if (need_drain) { 4079342SAndreas.Sandberg@arm.com drainManager = dm; 4088688Snilay@cs.wisc.edu 4099152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 4109342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 4119245Shestness@cs.wisc.edu return child_drain_count + 1; 4128688Snilay@cs.wisc.edu } 4138688Snilay@cs.wisc.edu 4149342SAndreas.Sandberg@arm.com drainManager = NULL; 4159342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 4169245Shestness@cs.wisc.edu return child_drain_count; 4176882SBrad.Beckmann@amd.com} 4186882SBrad.Beckmann@amd.com 4196882SBrad.Beckmann@amd.comvoid 4206882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 4216882SBrad.Beckmann@amd.com{ 4226882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4236882SBrad.Beckmann@amd.com 4247550SBrad.Beckmann@amd.com // 4257915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 4268184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 4277550SBrad.Beckmann@amd.com // 4287915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 4297550SBrad.Beckmann@amd.com 4307550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4317550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4327550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4337550SBrad.Beckmann@amd.com // 4347550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4357550SBrad.Beckmann@amd.com // 4367550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4377550SBrad.Beckmann@amd.com } else { 4387550SBrad.Beckmann@amd.com // 4397550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4407550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4417550SBrad.Beckmann@amd.com // 4427550SBrad.Beckmann@amd.com accessPhysMem = false; 4437550SBrad.Beckmann@amd.com } 4447550SBrad.Beckmann@amd.com } else { 4457550SBrad.Beckmann@amd.com // 4467550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4477550SBrad.Beckmann@amd.com // not lock the blocks. 4487550SBrad.Beckmann@amd.com // 4497550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4507550SBrad.Beckmann@amd.com } 4517550SBrad.Beckmann@amd.com } 4528184Ssomayeh@cs.wisc.edu 4538184Ssomayeh@cs.wisc.edu // 4548184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4558184Ssomayeh@cs.wisc.edu // 4568184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4578184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4588184Ssomayeh@cs.wisc.edu } 4598184Ssomayeh@cs.wisc.edu 4608161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4616882SBrad.Beckmann@amd.com 4627550SBrad.Beckmann@amd.com if (accessPhysMem) { 4638931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().access(pkt); 4648184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4657915SBrad.Beckmann@amd.com pkt->makeResponse(); 4667550SBrad.Beckmann@amd.com } 4676882SBrad.Beckmann@amd.com 4686882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4696882SBrad.Beckmann@amd.com if (needsResponse) { 4708161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4719163Sandreas.hansson@arm.com // send next cycle 4729206Snilay@cs.wisc.edu schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 4736882SBrad.Beckmann@amd.com } else { 4746882SBrad.Beckmann@amd.com delete pkt; 4756882SBrad.Beckmann@amd.com } 4768161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 4776882SBrad.Beckmann@amd.com} 4786882SBrad.Beckmann@amd.com 4798922Swilliam.wang@arm.comAddrRangeList 4809090Sandreas.hansson@arm.comRubyPort::M5Port::getAddrRanges() const 4818922Swilliam.wang@arm.com{ 4828922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 4838922Swilliam.wang@arm.com AddrRangeList ranges; 4848922Swilliam.wang@arm.com return ranges; 4858922Swilliam.wang@arm.com} 4868922Swilliam.wang@arm.com 4876882SBrad.Beckmann@amd.combool 4886882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 4896882SBrad.Beckmann@amd.com{ 4908931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 4916882SBrad.Beckmann@amd.com} 4927909Shestness@cs.utexas.edu 4937909Shestness@cs.utexas.eduunsigned 4947909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 4957909Shestness@cs.utexas.edu{ 4967909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 4977909Shestness@cs.utexas.edu} 4988717Snilay@cs.wisc.edu 4998717Snilay@cs.wisc.eduvoid 5008717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 5018717Snilay@cs.wisc.edu{ 5028717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 5038922Swilliam.wang@arm.com // should this really be using funcMasterId? 5048832SAli.Saidi@ARM.com Request req(address.getAddress(), 0, 0, Request::funcMasterId); 5058922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 5069088Sandreas.hansson@arm.com // check if the connected master port is snooping 5079088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 5088949Sandreas.hansson@arm.com Packet *pkt = new Packet(&req, MemCmd::InvalidationReq); 5098948Sandreas.hansson@arm.com // send as a snoop request 5108978Sandreas.hansson@arm.com (*p)->sendTimingSnoopReq(pkt); 5118922Swilliam.wang@arm.com } 5128717Snilay@cs.wisc.edu } 5138717Snilay@cs.wisc.edu} 514