RubyPort.cc revision 8874
16876Ssteve.reinhardt@amd.com/* 26876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 38717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 46876Ssteve.reinhardt@amd.com * All rights reserved. 56876Ssteve.reinhardt@amd.com * 66876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 76876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 86876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 96876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 106876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 116876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 126876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 136876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 146876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 156876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 166876Ssteve.reinhardt@amd.com * 176876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286876Ssteve.reinhardt@amd.com */ 296876Ssteve.reinhardt@amd.com 307632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 318688Snilay@cs.wisc.edu#include "debug/Config.hh" 328232Snate@binkert.org#include "debug/Ruby.hh" 338436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 347039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 356285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 366285Snate@binkert.org 376876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 388851Sandreas.hansson@arm.com : MemObject(p), pio_port(csprintf("%s-pio-port", name()), this), 398851Sandreas.hansson@arm.com physMemPort(csprintf("%s-physMemPort", name()), this) 406876Ssteve.reinhardt@amd.com{ 416876Ssteve.reinhardt@amd.com m_version = p->version; 426876Ssteve.reinhardt@amd.com assert(m_version != -1); 436876Ssteve.reinhardt@amd.com 446893SBrad.Beckmann@amd.com physmem = p->physmem; 457039Snate@binkert.org 466882SBrad.Beckmann@amd.com m_controller = NULL; 476882SBrad.Beckmann@amd.com m_mandatory_q_ptr = NULL; 486876Ssteve.reinhardt@amd.com 496876Ssteve.reinhardt@amd.com m_request_cnt = 0; 507910SBrad.Beckmann@amd.com 517910SBrad.Beckmann@amd.com m_usingRubyTester = p->using_ruby_tester; 527915SBrad.Beckmann@amd.com access_phys_mem = p->access_phys_mem; 538436SBrad.Beckmann@amd.com 548688Snilay@cs.wisc.edu drainEvent = NULL; 558688Snilay@cs.wisc.edu 568436SBrad.Beckmann@amd.com ruby_system = p->ruby_system; 578505Snilay@cs.wisc.edu waitingOnSequencer = false; 586876Ssteve.reinhardt@amd.com} 596876Ssteve.reinhardt@amd.com 607039Snate@binkert.orgvoid 617039Snate@binkert.orgRubyPort::init() 626882SBrad.Beckmann@amd.com{ 636882SBrad.Beckmann@amd.com assert(m_controller != NULL); 646882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 656882SBrad.Beckmann@amd.com} 666882SBrad.Beckmann@amd.com 676876Ssteve.reinhardt@amd.comPort * 686876Ssteve.reinhardt@amd.comRubyPort::getPort(const std::string &if_name, int idx) 696876Ssteve.reinhardt@amd.com{ 708839Sandreas.hansson@arm.com // used by the CPUs to connect the caches to the interconnect, and 718839Sandreas.hansson@arm.com // for the x86 case also the interrupt master 728839Sandreas.hansson@arm.com if (if_name == "slave") { 738839Sandreas.hansson@arm.com M5Port* cpuPort = new M5Port(csprintf("%s-slave%d", name(), idx), 748686Snilay@cs.wisc.edu this, ruby_system, access_phys_mem); 758686Snilay@cs.wisc.edu cpu_ports.push_back(cpuPort); 768686Snilay@cs.wisc.edu return cpuPort; 777039Snate@binkert.org } 787039Snate@binkert.org 798839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 808839Sandreas.hansson@arm.com // port 818839Sandreas.hansson@arm.com if (if_name == "master") { 828839Sandreas.hansson@arm.com PioPort* masterPort = new PioPort(csprintf("%s-master%d", name(), idx), 838839Sandreas.hansson@arm.com this); 848839Sandreas.hansson@arm.com 858839Sandreas.hansson@arm.com return masterPort; 868839Sandreas.hansson@arm.com } 878839Sandreas.hansson@arm.com 887039Snate@binkert.org if (if_name == "pio_port") { 898851Sandreas.hansson@arm.com return &pio_port; 907039Snate@binkert.org } 917039Snate@binkert.org 927039Snate@binkert.org if (if_name == "physMemPort") { 938851Sandreas.hansson@arm.com return &physMemPort; 947039Snate@binkert.org } 957039Snate@binkert.org 966876Ssteve.reinhardt@amd.com return NULL; 976876Ssteve.reinhardt@amd.com} 986882SBrad.Beckmann@amd.com 997039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1006882SBrad.Beckmann@amd.com RubyPort *_port) 1016882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1026882SBrad.Beckmann@amd.com{ 1038161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name); 1046882SBrad.Beckmann@amd.com ruby_port = _port; 1056882SBrad.Beckmann@amd.com} 1066882SBrad.Beckmann@amd.com 1078436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1088436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1096882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1106882SBrad.Beckmann@amd.com{ 1118161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name); 1126882SBrad.Beckmann@amd.com ruby_port = _port; 1138436SBrad.Beckmann@amd.com ruby_system = _system; 1147910SBrad.Beckmann@amd.com _onRetryList = false; 1157915SBrad.Beckmann@amd.com access_phys_mem = _access_phys_mem; 1166882SBrad.Beckmann@amd.com} 1176882SBrad.Beckmann@amd.com 1186882SBrad.Beckmann@amd.comTick 1196882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1206882SBrad.Beckmann@amd.com{ 1216882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1226882SBrad.Beckmann@amd.com return 0; 1236882SBrad.Beckmann@amd.com} 1246882SBrad.Beckmann@amd.com 1256882SBrad.Beckmann@amd.comTick 1266882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1276882SBrad.Beckmann@amd.com{ 1286882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1296882SBrad.Beckmann@amd.com return 0; 1306882SBrad.Beckmann@amd.com} 1316882SBrad.Beckmann@amd.com 1326882SBrad.Beckmann@amd.com 1336882SBrad.Beckmann@amd.combool 1346882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1356882SBrad.Beckmann@amd.com{ 1367039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1377039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1388161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1396882SBrad.Beckmann@amd.com 1406882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1416882SBrad.Beckmann@amd.com 1426882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1437039Snate@binkert.org RubyPort::SenderState *senderState = 1446882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1456882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1466882SBrad.Beckmann@amd.com assert(port != NULL); 1477039Snate@binkert.org 1486882SBrad.Beckmann@amd.com // pop the sender state from the packet 1496882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1506882SBrad.Beckmann@amd.com delete senderState; 1517039Snate@binkert.org 1526882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1537039Snate@binkert.org 1546882SBrad.Beckmann@amd.com return true; 1556882SBrad.Beckmann@amd.com} 1566882SBrad.Beckmann@amd.com 1576882SBrad.Beckmann@amd.combool 1586882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1596882SBrad.Beckmann@amd.com{ 1608161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1617039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1626882SBrad.Beckmann@amd.com 1636882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1646882SBrad.Beckmann@amd.com 1657039Snate@binkert.org // The received packets should only be M5 requests, which should never 1667039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1677039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1686882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1696882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1706882SBrad.Beckmann@amd.com 1716882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1726882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1736882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1746882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1756882SBrad.Beckmann@amd.com delete pkt; 1766882SBrad.Beckmann@amd.com return true; 1776882SBrad.Beckmann@amd.com } 1786882SBrad.Beckmann@amd.com 1796922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1806922SBrad.Beckmann@amd.com // route the response 1816922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1826922SBrad.Beckmann@amd.com 1836882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1846882SBrad.Beckmann@amd.com // pio port. 1856882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1868851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 1878161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1886922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1896922SBrad.Beckmann@amd.com pkt->getAddr()); 1906882SBrad.Beckmann@amd.com 1918874Sandreas.hansson@arm.com return ruby_port->pio_port.sendNextCycle(pkt); 1926882SBrad.Beckmann@amd.com } 1936882SBrad.Beckmann@amd.com 1948615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 1958615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 1967906SBrad.Beckmann@amd.com 1976882SBrad.Beckmann@amd.com // Submit the ruby request 1988615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 1997023SBrad.Beckmann@amd.com 2007550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2017023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2027023SBrad.Beckmann@amd.com // false. 2037550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2048161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2056922SBrad.Beckmann@amd.com return true; 2066882SBrad.Beckmann@amd.com } 2077023SBrad.Beckmann@amd.com 2087910SBrad.Beckmann@amd.com // 2097910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2107910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2117910SBrad.Beckmann@amd.com // 2127910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2137910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2147910SBrad.Beckmann@amd.com } 2157910SBrad.Beckmann@amd.com 2168161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2177906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2187039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2197039Snate@binkert.org 2206922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2216922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2226922SBrad.Beckmann@amd.com delete senderState; 2236922SBrad.Beckmann@amd.com return false; 2246882SBrad.Beckmann@amd.com} 2256882SBrad.Beckmann@amd.com 2268436SBrad.Beckmann@amd.combool 2278436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 2288436SBrad.Beckmann@amd.com{ 2298436SBrad.Beckmann@amd.com Address address(pkt->getAddr()); 2308436SBrad.Beckmann@amd.com Address line_address(address); 2318436SBrad.Beckmann@amd.com line_address.makeLineAddress(); 2328436SBrad.Beckmann@amd.com 2338532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 2348436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 2358436SBrad.Beckmann@amd.com 2368532SLisa.Hsu@amd.com DPRINTF(RubyPort, "Functional Read request for %s\n",address); 2378436SBrad.Beckmann@amd.com 2388532SLisa.Hsu@amd.com unsigned int num_ro = 0; 2398532SLisa.Hsu@amd.com unsigned int num_rw = 0; 2408532SLisa.Hsu@amd.com unsigned int num_busy = 0; 2418532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 2428532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 2438532SLisa.Hsu@amd.com 2448532SLisa.Hsu@amd.com // In this loop we count the number of controllers that have the given 2458532SLisa.Hsu@amd.com // address in read only, read write and busy states. 2468532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 2478532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 2488532SLisa.Hsu@amd.com getAccessPermission(line_address); 2498532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 2508532SLisa.Hsu@amd.com num_ro++; 2518532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 2528532SLisa.Hsu@amd.com num_rw++; 2538532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 2548532SLisa.Hsu@amd.com num_busy++; 2558532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 2568532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 2578532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 2588532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 2598532SLisa.Hsu@amd.com // or not. 2608532SLisa.Hsu@amd.com num_backing_store++; 2618532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 2628532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 2638532SLisa.Hsu@amd.com num_invalid++; 2648532SLisa.Hsu@amd.com } 2658532SLisa.Hsu@amd.com assert(num_rw <= 1); 2668532SLisa.Hsu@amd.com 2678532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 2688532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 2698532SLisa.Hsu@amd.com unsigned startByte = address.getAddress() - line_address.getAddress(); 2708532SLisa.Hsu@amd.com 2718532SLisa.Hsu@amd.com // This if case is meant to capture what happens in a Broadcast/Snoop 2728532SLisa.Hsu@amd.com // protocol where the block does not exist in the cache hierarchy. You 2738532SLisa.Hsu@amd.com // only want to read from the Backing_Store memory if there is no copy in 2748532SLisa.Hsu@amd.com // the cache hierarchy, otherwise you want to try to read the RO or RW 2758532SLisa.Hsu@amd.com // copies existing in the cache hierarchy (covered by the else statement). 2768532SLisa.Hsu@amd.com // The reason is because the Backing_Store memory could easily be stale, if 2778532SLisa.Hsu@amd.com // there are copies floating around the cache hierarchy, so you want to read 2788532SLisa.Hsu@amd.com // it only if it's not in the cache hierarchy at all. 2798532SLisa.Hsu@amd.com if (num_invalid == (num_controllers - 1) && 2808532SLisa.Hsu@amd.com num_backing_store == 1) 2818436SBrad.Beckmann@amd.com { 2828532SLisa.Hsu@amd.com DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 2838532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 2848532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 2858532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 2868532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Backing_Store) { 2878532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 2888436SBrad.Beckmann@amd.com ->getDataBlock(line_address); 2898436SBrad.Beckmann@amd.com 2908532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 2918532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 2928532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 2938532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 2948532SLisa.Hsu@amd.com } 2958532SLisa.Hsu@amd.com return true; 2968532SLisa.Hsu@amd.com } 2978532SLisa.Hsu@amd.com } 2988532SLisa.Hsu@amd.com } else { 2998532SLisa.Hsu@amd.com // In Broadcast/Snoop protocols, this covers if you know the block 3008532SLisa.Hsu@amd.com // exists somewhere in the caching hierarchy, then you want to read any 3018532SLisa.Hsu@amd.com // valid RO or RW block. In directory protocols, same thing, you want 3028532SLisa.Hsu@amd.com // to read any valid readable copy of the block. 3038532SLisa.Hsu@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3048532SLisa.Hsu@amd.com num_busy, num_ro, num_rw); 3058532SLisa.Hsu@amd.com // In this loop, we try to figure which controller has a read only or 3068532SLisa.Hsu@amd.com // a read write copy of the given address. Any valid copy would suffice 3078532SLisa.Hsu@amd.com // for a functional read. 3088532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3098532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3108532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3118532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3128532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write) 3138436SBrad.Beckmann@amd.com { 3148532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3158532SLisa.Hsu@amd.com ->getDataBlock(line_address); 3168532SLisa.Hsu@amd.com 3178532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3188532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3198532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3208532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3218532SLisa.Hsu@amd.com } 3228532SLisa.Hsu@amd.com return true; 3238436SBrad.Beckmann@amd.com } 3248436SBrad.Beckmann@amd.com } 3258436SBrad.Beckmann@amd.com } 3268436SBrad.Beckmann@amd.com return false; 3278436SBrad.Beckmann@amd.com} 3288436SBrad.Beckmann@amd.com 3298436SBrad.Beckmann@amd.combool 3308436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 3318436SBrad.Beckmann@amd.com{ 3328436SBrad.Beckmann@amd.com Address addr(pkt->getAddr()); 3338436SBrad.Beckmann@amd.com Address line_addr = line_address(addr); 3348532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 3358436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3368436SBrad.Beckmann@amd.com 3378436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 3388436SBrad.Beckmann@amd.com 3398436SBrad.Beckmann@amd.com unsigned int num_ro = 0; 3408436SBrad.Beckmann@amd.com unsigned int num_rw = 0; 3418436SBrad.Beckmann@amd.com unsigned int num_busy = 0; 3428532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 3438532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 3448436SBrad.Beckmann@amd.com 3458436SBrad.Beckmann@amd.com // In this loop we count the number of controllers that have the given 3468436SBrad.Beckmann@amd.com // address in read only, read write and busy states. 3478532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3488532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3498436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3508532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 3518532SLisa.Hsu@amd.com num_ro++; 3528532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 3538532SLisa.Hsu@amd.com num_rw++; 3548532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 3558532SLisa.Hsu@amd.com num_busy++; 3568532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 3578532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 3588532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 3598532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 3608532SLisa.Hsu@amd.com // or not. 3618532SLisa.Hsu@amd.com num_backing_store++; 3628532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 3638532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 3648532SLisa.Hsu@amd.com num_invalid++; 3658436SBrad.Beckmann@amd.com } 3668436SBrad.Beckmann@amd.com 3678436SBrad.Beckmann@amd.com // If the number of read write copies is more than 1, then there is bug in 3688436SBrad.Beckmann@amd.com // coherence protocol. Otherwise, if all copies are in stable states, i.e. 3698436SBrad.Beckmann@amd.com // num_busy == 0, we update all the copies. If there is at least one copy 3708436SBrad.Beckmann@amd.com // in busy state, then we check if there is read write copy. If yes, then 3718532SLisa.Hsu@amd.com // also we let the access go through. Or, if there is no copy in the cache 3728532SLisa.Hsu@amd.com // hierarchy at all, we still want to do the write to the memory 3738532SLisa.Hsu@amd.com // (Backing_Store) instead of failing. 3748436SBrad.Beckmann@amd.com 3758436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3768436SBrad.Beckmann@amd.com num_busy, num_ro, num_rw); 3778436SBrad.Beckmann@amd.com assert(num_rw <= 1); 3788532SLisa.Hsu@amd.com 3798532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3808532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 3818532SLisa.Hsu@amd.com unsigned startByte = addr.getAddress() - line_addr.getAddress(); 3828532SLisa.Hsu@amd.com 3838532SLisa.Hsu@amd.com if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 3848532SLisa.Hsu@amd.com (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 3858436SBrad.Beckmann@amd.com { 3868532SLisa.Hsu@amd.com for(int i = 0; i < num_controllers;++i) { 3878532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3888436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3898532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3908532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write|| 3918532SLisa.Hsu@amd.com access_perm == AccessPermission_Maybe_Stale || 3928532SLisa.Hsu@amd.com access_perm == AccessPermission_Backing_Store) 3938436SBrad.Beckmann@amd.com { 3948436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3958436SBrad.Beckmann@amd.com ->getDataBlock(line_addr); 3968436SBrad.Beckmann@amd.com 3978436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 3988532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3998436SBrad.Beckmann@amd.com block.setByte(i + startByte, data[i]); 4008436SBrad.Beckmann@amd.com } 4018436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4028436SBrad.Beckmann@amd.com } 4038436SBrad.Beckmann@amd.com } 4048436SBrad.Beckmann@amd.com return true; 4058436SBrad.Beckmann@amd.com } 4068436SBrad.Beckmann@amd.com return false; 4078436SBrad.Beckmann@amd.com} 4088436SBrad.Beckmann@amd.com 4098436SBrad.Beckmann@amd.comvoid 4108436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 4118436SBrad.Beckmann@amd.com{ 4128436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 4138436SBrad.Beckmann@amd.com pkt->getAddr()); 4148436SBrad.Beckmann@amd.com 4158436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 4168436SBrad.Beckmann@amd.com // pio port. 4178436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 4188851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 4198436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 4208436SBrad.Beckmann@amd.com pkt->getAddr()); 4218436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 4228436SBrad.Beckmann@amd.com } 4238436SBrad.Beckmann@amd.com 4248436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 4258436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 4268436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 4278436SBrad.Beckmann@amd.com 4288436SBrad.Beckmann@amd.com bool accessSucceeded = false; 4298436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4308436SBrad.Beckmann@amd.com 4318436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 4328436SBrad.Beckmann@amd.com if (pkt->isRead()) { 4338436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalRead(pkt); 4348436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 4358436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalWrite(pkt); 4368436SBrad.Beckmann@amd.com } else { 4378436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 4388436SBrad.Beckmann@amd.com pkt->cmdString()); 4398436SBrad.Beckmann@amd.com } 4408436SBrad.Beckmann@amd.com 4418436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 4428436SBrad.Beckmann@amd.com // the functional request failed 4438436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 4448436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 4458436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 4468436SBrad.Beckmann@amd.com } 4478436SBrad.Beckmann@amd.com 4488436SBrad.Beckmann@amd.com if (access_phys_mem) { 4498436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 4508436SBrad.Beckmann@amd.com // The following command performs the real functional access. 4518436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 4528436SBrad.Beckmann@amd.com // of data. 4538851Sandreas.hansson@arm.com ruby_port->physMemPort.sendFunctional(pkt); 4548436SBrad.Beckmann@amd.com } 4558436SBrad.Beckmann@amd.com 4568436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4578436SBrad.Beckmann@amd.com if (needsResponse) { 4588436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 4598706Sandreas.hansson@arm.com 4608706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 4618706Sandreas.hansson@arm.com // communicated through the packet pointer 4628706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 4638706Sandreas.hansson@arm.com // sendFunctional(pkt); 4648436SBrad.Beckmann@amd.com } 4658436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 4668436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 4678436SBrad.Beckmann@amd.com} 4688436SBrad.Beckmann@amd.com 4696882SBrad.Beckmann@amd.comvoid 4706922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 4716882SBrad.Beckmann@amd.com{ 4726922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 4737039Snate@binkert.org RubyPort::SenderState *senderState = 4746922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 4756922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 4766922SBrad.Beckmann@amd.com assert(port != NULL); 4777039Snate@binkert.org 4786922SBrad.Beckmann@amd.com // pop the sender state from the packet 4796922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 4806922SBrad.Beckmann@amd.com delete senderState; 4816882SBrad.Beckmann@amd.com 4826882SBrad.Beckmann@amd.com port->hitCallback(pkt); 4837910SBrad.Beckmann@amd.com 4847910SBrad.Beckmann@amd.com // 4857910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 4867910SBrad.Beckmann@amd.com // likely has free resources now. 4877910SBrad.Beckmann@amd.com // 4887910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 4898162SBrad.Beckmann@amd.com // 4908162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 4918162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 4928162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 4938162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 4948162SBrad.Beckmann@amd.com // sendRetry. 4958162SBrad.Beckmann@amd.com // 4968162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 4978162SBrad.Beckmann@amd.com 4988162SBrad.Beckmann@amd.com retryList.clear(); 4998162SBrad.Beckmann@amd.com waitingOnSequencer = false; 5008162SBrad.Beckmann@amd.com 5018162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 5028162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 5038162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 5047910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 5057910SBrad.Beckmann@amd.com (*i)->name()); 5068162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 5078162SBrad.Beckmann@amd.com (*i)->sendRetry(); 5087910SBrad.Beckmann@amd.com } 5097910SBrad.Beckmann@amd.com } 5108688Snilay@cs.wisc.edu 5118688Snilay@cs.wisc.edu testDrainComplete(); 5128688Snilay@cs.wisc.edu} 5138688Snilay@cs.wisc.edu 5148688Snilay@cs.wisc.eduvoid 5158688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 5168688Snilay@cs.wisc.edu{ 5178688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 5188688Snilay@cs.wisc.edu if (drainEvent != NULL) { 5198688Snilay@cs.wisc.edu unsigned int drainCount = getDrainCount(drainEvent); 5208688Snilay@cs.wisc.edu DPRINTF(Config, "Drain count: %u\n", drainCount); 5218688Snilay@cs.wisc.edu if (drainCount == 0) { 5228688Snilay@cs.wisc.edu drainEvent->process(); 5238688Snilay@cs.wisc.edu // Clear the drain event once we're done with it. 5248688Snilay@cs.wisc.edu drainEvent = NULL; 5258688Snilay@cs.wisc.edu } 5268688Snilay@cs.wisc.edu } 5278688Snilay@cs.wisc.edu} 5288688Snilay@cs.wisc.edu 5298688Snilay@cs.wisc.eduunsigned int 5308688Snilay@cs.wisc.eduRubyPort::getDrainCount(Event *de) 5318688Snilay@cs.wisc.edu{ 5328688Snilay@cs.wisc.edu int count = 0; 5338688Snilay@cs.wisc.edu // 5348688Snilay@cs.wisc.edu // If the sequencer is not empty, then requests need to drain. 5358688Snilay@cs.wisc.edu // The outstandingCount is the number of requests outstanding and thus the 5368688Snilay@cs.wisc.edu // number of times M5's timing port will process the drain event. 5378688Snilay@cs.wisc.edu // 5388688Snilay@cs.wisc.edu count += outstandingCount(); 5398688Snilay@cs.wisc.edu 5408688Snilay@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 5418688Snilay@cs.wisc.edu 5428688Snilay@cs.wisc.edu // To simplify the draining process, the sequencer's deadlock detection 5438688Snilay@cs.wisc.edu // event should have been descheduled. 5448688Snilay@cs.wisc.edu assert(isDeadlockEventScheduled() == false); 5458688Snilay@cs.wisc.edu 5468851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 5478851Sandreas.hansson@arm.com count += pio_port.drain(de); 5488688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 5498688Snilay@cs.wisc.edu } 5508851Sandreas.hansson@arm.com if (physMemPort.isConnected()) { 5518851Sandreas.hansson@arm.com count += physMemPort.drain(de); 5528688Snilay@cs.wisc.edu DPRINTF(Config, "count after physmem check %d\n", count); 5538688Snilay@cs.wisc.edu } 5548688Snilay@cs.wisc.edu 5558688Snilay@cs.wisc.edu for (CpuPortIter p_iter = cpu_ports.begin(); p_iter != cpu_ports.end(); 5568688Snilay@cs.wisc.edu p_iter++) { 5578688Snilay@cs.wisc.edu M5Port* cpu_port = *p_iter; 5588688Snilay@cs.wisc.edu count += cpu_port->drain(de); 5598688Snilay@cs.wisc.edu DPRINTF(Config, "count after cpu port check %d\n", count); 5608688Snilay@cs.wisc.edu } 5618688Snilay@cs.wisc.edu 5628688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 5638688Snilay@cs.wisc.edu 5648688Snilay@cs.wisc.edu return count; 5658688Snilay@cs.wisc.edu} 5668688Snilay@cs.wisc.edu 5678688Snilay@cs.wisc.eduunsigned int 5688688Snilay@cs.wisc.eduRubyPort::drain(Event *de) 5698688Snilay@cs.wisc.edu{ 5708688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 5718688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 5728688Snilay@cs.wisc.edu } 5738688Snilay@cs.wisc.edu 5748688Snilay@cs.wisc.edu int count = getDrainCount(de); 5758688Snilay@cs.wisc.edu 5768688Snilay@cs.wisc.edu // Set status 5778688Snilay@cs.wisc.edu if (count != 0) { 5788688Snilay@cs.wisc.edu drainEvent = de; 5798688Snilay@cs.wisc.edu 5808688Snilay@cs.wisc.edu changeState(SimObject::Draining); 5818688Snilay@cs.wisc.edu return count; 5828688Snilay@cs.wisc.edu } 5838688Snilay@cs.wisc.edu 5848688Snilay@cs.wisc.edu changeState(SimObject::Drained); 5858688Snilay@cs.wisc.edu return 0; 5866882SBrad.Beckmann@amd.com} 5876882SBrad.Beckmann@amd.com 5886882SBrad.Beckmann@amd.comvoid 5896882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 5906882SBrad.Beckmann@amd.com{ 5916882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 5926882SBrad.Beckmann@amd.com 5937550SBrad.Beckmann@amd.com // 5947915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 5958184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 5967550SBrad.Beckmann@amd.com // 5977915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 5987550SBrad.Beckmann@amd.com 5997550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 6007550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 6017550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 6027550SBrad.Beckmann@amd.com // 6037550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 6047550SBrad.Beckmann@amd.com // 6057550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 6067550SBrad.Beckmann@amd.com } else { 6077550SBrad.Beckmann@amd.com // 6087550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 6097550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 6107550SBrad.Beckmann@amd.com // 6117550SBrad.Beckmann@amd.com accessPhysMem = false; 6127550SBrad.Beckmann@amd.com } 6137550SBrad.Beckmann@amd.com } else { 6147550SBrad.Beckmann@amd.com // 6157550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 6167550SBrad.Beckmann@amd.com // not lock the blocks. 6177550SBrad.Beckmann@amd.com // 6187550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 6197550SBrad.Beckmann@amd.com } 6207550SBrad.Beckmann@amd.com } 6218184Ssomayeh@cs.wisc.edu 6228184Ssomayeh@cs.wisc.edu // 6238184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 6248184Ssomayeh@cs.wisc.edu // 6258184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 6268184Ssomayeh@cs.wisc.edu accessPhysMem = false; 6278184Ssomayeh@cs.wisc.edu } 6288184Ssomayeh@cs.wisc.edu 6298161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 6306882SBrad.Beckmann@amd.com 6317550SBrad.Beckmann@amd.com if (accessPhysMem) { 6328851Sandreas.hansson@arm.com ruby_port->physMemPort.sendAtomic(pkt); 6338184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 6347915SBrad.Beckmann@amd.com pkt->makeResponse(); 6357550SBrad.Beckmann@amd.com } 6366882SBrad.Beckmann@amd.com 6376882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 6386882SBrad.Beckmann@amd.com if (needsResponse) { 6398161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 6408874Sandreas.hansson@arm.com sendNextCycle(pkt); 6416882SBrad.Beckmann@amd.com } else { 6426882SBrad.Beckmann@amd.com delete pkt; 6436882SBrad.Beckmann@amd.com } 6448161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 6456882SBrad.Beckmann@amd.com} 6466882SBrad.Beckmann@amd.com 6476882SBrad.Beckmann@amd.combool 6488874Sandreas.hansson@arm.comRubyPort::M5Port::sendNextCycle(PacketPtr pkt) 6496882SBrad.Beckmann@amd.com{ 6507558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6517823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6526882SBrad.Beckmann@amd.com return true; 6536882SBrad.Beckmann@amd.com} 6546882SBrad.Beckmann@amd.com 6556882SBrad.Beckmann@amd.combool 6568874Sandreas.hansson@arm.comRubyPort::PioPort::sendNextCycle(PacketPtr pkt) 6576882SBrad.Beckmann@amd.com{ 6587558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6597823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6606882SBrad.Beckmann@amd.com return true; 6616882SBrad.Beckmann@amd.com} 6626882SBrad.Beckmann@amd.com 6636882SBrad.Beckmann@amd.combool 6646882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 6656882SBrad.Beckmann@amd.com{ 6668711Sandreas.hansson@arm.com AddrRangeList physMemAddrList = 6678851Sandreas.hansson@arm.com ruby_port->physMemPort.getPeer()->getAddrRanges(); 6687039Snate@binkert.org for (AddrRangeIter iter = physMemAddrList.begin(); 6697039Snate@binkert.org iter != physMemAddrList.end(); 6707039Snate@binkert.org iter++) { 6716882SBrad.Beckmann@amd.com if (addr >= iter->start && addr <= iter->end) { 6728161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 6736882SBrad.Beckmann@amd.com iter->start, iter->end); 6746882SBrad.Beckmann@amd.com return true; 6756882SBrad.Beckmann@amd.com } 6766882SBrad.Beckmann@amd.com } 6776882SBrad.Beckmann@amd.com return false; 6786882SBrad.Beckmann@amd.com} 6797909Shestness@cs.utexas.edu 6807909Shestness@cs.utexas.eduunsigned 6817909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 6827909Shestness@cs.utexas.edu{ 6837909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 6847909Shestness@cs.utexas.edu} 6858717Snilay@cs.wisc.edu 6868717Snilay@cs.wisc.eduvoid 6878717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 6888717Snilay@cs.wisc.edu{ 6898717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 6908832SAli.Saidi@ARM.com Request req(address.getAddress(), 0, 0, Request::funcMasterId); 6918717Snilay@cs.wisc.edu for (CpuPortIter it = cpu_ports.begin(); it != cpu_ports.end(); it++) { 6928717Snilay@cs.wisc.edu Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1); 6938874Sandreas.hansson@arm.com (*it)->sendNextCycle(pkt); 6948717Snilay@cs.wisc.edu } 6958717Snilay@cs.wisc.edu} 696