RubyPort.cc revision 8686
16876Ssteve.reinhardt@amd.com/* 26876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 36876Ssteve.reinhardt@amd.com * All rights reserved. 46876Ssteve.reinhardt@amd.com * 56876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 66876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 76876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 86876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 96876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 106876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 126876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 136876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 146876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 156876Ssteve.reinhardt@amd.com * 166876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276876Ssteve.reinhardt@amd.com */ 286876Ssteve.reinhardt@amd.com 297632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 308232Snate@binkert.org#include "debug/Ruby.hh" 318436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 327039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 336285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 348229Snate@binkert.org#include "mem/physical.hh" 356285Snate@binkert.org 366876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 376893SBrad.Beckmann@amd.com : MemObject(p) 386876Ssteve.reinhardt@amd.com{ 396876Ssteve.reinhardt@amd.com m_version = p->version; 406876Ssteve.reinhardt@amd.com assert(m_version != -1); 416876Ssteve.reinhardt@amd.com 426893SBrad.Beckmann@amd.com physmem = p->physmem; 437039Snate@binkert.org 446882SBrad.Beckmann@amd.com m_controller = NULL; 456882SBrad.Beckmann@amd.com m_mandatory_q_ptr = NULL; 466876Ssteve.reinhardt@amd.com 476876Ssteve.reinhardt@amd.com m_request_cnt = 0; 486882SBrad.Beckmann@amd.com pio_port = NULL; 496893SBrad.Beckmann@amd.com physMemPort = NULL; 507910SBrad.Beckmann@amd.com 517910SBrad.Beckmann@amd.com m_usingRubyTester = p->using_ruby_tester; 527915SBrad.Beckmann@amd.com access_phys_mem = p->access_phys_mem; 538436SBrad.Beckmann@amd.com 548436SBrad.Beckmann@amd.com ruby_system = p->ruby_system; 558505Snilay@cs.wisc.edu waitingOnSequencer = false; 566876Ssteve.reinhardt@amd.com} 576876Ssteve.reinhardt@amd.com 587039Snate@binkert.orgvoid 597039Snate@binkert.orgRubyPort::init() 606882SBrad.Beckmann@amd.com{ 616882SBrad.Beckmann@amd.com assert(m_controller != NULL); 626882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 636882SBrad.Beckmann@amd.com} 646882SBrad.Beckmann@amd.com 656876Ssteve.reinhardt@amd.comPort * 666876Ssteve.reinhardt@amd.comRubyPort::getPort(const std::string &if_name, int idx) 676876Ssteve.reinhardt@amd.com{ 686882SBrad.Beckmann@amd.com if (if_name == "port") { 698686Snilay@cs.wisc.edu M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx), 708686Snilay@cs.wisc.edu this, ruby_system, access_phys_mem); 718686Snilay@cs.wisc.edu cpu_ports.push_back(cpuPort); 728686Snilay@cs.wisc.edu return cpuPort; 737039Snate@binkert.org } 747039Snate@binkert.org 757039Snate@binkert.org if (if_name == "pio_port") { 766882SBrad.Beckmann@amd.com // ensure there is only one pio port 776882SBrad.Beckmann@amd.com assert(pio_port == NULL); 786882SBrad.Beckmann@amd.com 797039Snate@binkert.org pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this); 806882SBrad.Beckmann@amd.com 816882SBrad.Beckmann@amd.com return pio_port; 827039Snate@binkert.org } 837039Snate@binkert.org 847039Snate@binkert.org if (if_name == "physMemPort") { 856893SBrad.Beckmann@amd.com // RubyPort should only have one port to physical memory 866893SBrad.Beckmann@amd.com assert (physMemPort == NULL); 876893SBrad.Beckmann@amd.com 887915SBrad.Beckmann@amd.com physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, 898436SBrad.Beckmann@amd.com ruby_system, access_phys_mem); 907039Snate@binkert.org 916893SBrad.Beckmann@amd.com return physMemPort; 927039Snate@binkert.org } 937039Snate@binkert.org 947039Snate@binkert.org if (if_name == "functional") { 957039Snate@binkert.org // Calls for the functional port only want to access 967039Snate@binkert.org // functional memory. Therefore, directly pass these calls 977039Snate@binkert.org // ports to physmem. 986893SBrad.Beckmann@amd.com assert(physmem != NULL); 996893SBrad.Beckmann@amd.com return physmem->getPort(if_name, idx); 1006882SBrad.Beckmann@amd.com } 1017039Snate@binkert.org 1026876Ssteve.reinhardt@amd.com return NULL; 1036876Ssteve.reinhardt@amd.com} 1046882SBrad.Beckmann@amd.com 1057039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1066882SBrad.Beckmann@amd.com RubyPort *_port) 1076882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1086882SBrad.Beckmann@amd.com{ 1098161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name); 1106882SBrad.Beckmann@amd.com ruby_port = _port; 1116882SBrad.Beckmann@amd.com} 1126882SBrad.Beckmann@amd.com 1138436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1148436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1156882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1166882SBrad.Beckmann@amd.com{ 1178161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name); 1186882SBrad.Beckmann@amd.com ruby_port = _port; 1198436SBrad.Beckmann@amd.com ruby_system = _system; 1207910SBrad.Beckmann@amd.com _onRetryList = false; 1217915SBrad.Beckmann@amd.com access_phys_mem = _access_phys_mem; 1226882SBrad.Beckmann@amd.com} 1236882SBrad.Beckmann@amd.com 1246882SBrad.Beckmann@amd.comTick 1256882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1266882SBrad.Beckmann@amd.com{ 1276882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1286882SBrad.Beckmann@amd.com return 0; 1296882SBrad.Beckmann@amd.com} 1306882SBrad.Beckmann@amd.com 1316882SBrad.Beckmann@amd.comTick 1326882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1336882SBrad.Beckmann@amd.com{ 1346882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1356882SBrad.Beckmann@amd.com return 0; 1366882SBrad.Beckmann@amd.com} 1376882SBrad.Beckmann@amd.com 1386882SBrad.Beckmann@amd.com 1396882SBrad.Beckmann@amd.combool 1406882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1416882SBrad.Beckmann@amd.com{ 1427039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1437039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1448161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1456882SBrad.Beckmann@amd.com 1466882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1476882SBrad.Beckmann@amd.com 1486882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1497039Snate@binkert.org RubyPort::SenderState *senderState = 1506882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1516882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1526882SBrad.Beckmann@amd.com assert(port != NULL); 1537039Snate@binkert.org 1546882SBrad.Beckmann@amd.com // pop the sender state from the packet 1556882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1566882SBrad.Beckmann@amd.com delete senderState; 1577039Snate@binkert.org 1586882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1597039Snate@binkert.org 1606882SBrad.Beckmann@amd.com return true; 1616882SBrad.Beckmann@amd.com} 1626882SBrad.Beckmann@amd.com 1636882SBrad.Beckmann@amd.combool 1646882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1656882SBrad.Beckmann@amd.com{ 1668161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1677039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1686882SBrad.Beckmann@amd.com 1696882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1706882SBrad.Beckmann@amd.com 1717039Snate@binkert.org // The received packets should only be M5 requests, which should never 1727039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1737039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1746882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1756882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1766882SBrad.Beckmann@amd.com 1776882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1786882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1796882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1806882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1816882SBrad.Beckmann@amd.com delete pkt; 1826882SBrad.Beckmann@amd.com return true; 1836882SBrad.Beckmann@amd.com } 1846882SBrad.Beckmann@amd.com 1856922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1866922SBrad.Beckmann@amd.com // route the response 1876922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1886922SBrad.Beckmann@amd.com 1896882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1906882SBrad.Beckmann@amd.com // pio port. 1916882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1926882SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 1938161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1946922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1956922SBrad.Beckmann@amd.com pkt->getAddr()); 1966882SBrad.Beckmann@amd.com 1976882SBrad.Beckmann@amd.com return ruby_port->pio_port->sendTiming(pkt); 1986882SBrad.Beckmann@amd.com } 1996882SBrad.Beckmann@amd.com 2008615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 2018615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2027906SBrad.Beckmann@amd.com 2036882SBrad.Beckmann@amd.com // Submit the ruby request 2048615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2057023SBrad.Beckmann@amd.com 2067550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2077023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2087023SBrad.Beckmann@amd.com // false. 2097550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2108161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2116922SBrad.Beckmann@amd.com return true; 2126882SBrad.Beckmann@amd.com } 2137023SBrad.Beckmann@amd.com 2147910SBrad.Beckmann@amd.com // 2157910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2167910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2177910SBrad.Beckmann@amd.com // 2187910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2197910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2207910SBrad.Beckmann@amd.com } 2217910SBrad.Beckmann@amd.com 2228161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2237906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2247039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2257039Snate@binkert.org 2266922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2276922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2286922SBrad.Beckmann@amd.com delete senderState; 2296922SBrad.Beckmann@amd.com return false; 2306882SBrad.Beckmann@amd.com} 2316882SBrad.Beckmann@amd.com 2328436SBrad.Beckmann@amd.combool 2338436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 2348436SBrad.Beckmann@amd.com{ 2358436SBrad.Beckmann@amd.com Address address(pkt->getAddr()); 2368436SBrad.Beckmann@amd.com Address line_address(address); 2378436SBrad.Beckmann@amd.com line_address.makeLineAddress(); 2388436SBrad.Beckmann@amd.com 2398532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 2408436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 2418436SBrad.Beckmann@amd.com 2428532SLisa.Hsu@amd.com DPRINTF(RubyPort, "Functional Read request for %s\n",address); 2438436SBrad.Beckmann@amd.com 2448532SLisa.Hsu@amd.com unsigned int num_ro = 0; 2458532SLisa.Hsu@amd.com unsigned int num_rw = 0; 2468532SLisa.Hsu@amd.com unsigned int num_busy = 0; 2478532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 2488532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 2498532SLisa.Hsu@amd.com 2508532SLisa.Hsu@amd.com // In this loop we count the number of controllers that have the given 2518532SLisa.Hsu@amd.com // address in read only, read write and busy states. 2528532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 2538532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 2548532SLisa.Hsu@amd.com getAccessPermission(line_address); 2558532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 2568532SLisa.Hsu@amd.com num_ro++; 2578532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 2588532SLisa.Hsu@amd.com num_rw++; 2598532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 2608532SLisa.Hsu@amd.com num_busy++; 2618532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 2628532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 2638532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 2648532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 2658532SLisa.Hsu@amd.com // or not. 2668532SLisa.Hsu@amd.com num_backing_store++; 2678532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 2688532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 2698532SLisa.Hsu@amd.com num_invalid++; 2708532SLisa.Hsu@amd.com } 2718532SLisa.Hsu@amd.com assert(num_rw <= 1); 2728532SLisa.Hsu@amd.com 2738532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 2748532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 2758532SLisa.Hsu@amd.com unsigned startByte = address.getAddress() - line_address.getAddress(); 2768532SLisa.Hsu@amd.com 2778532SLisa.Hsu@amd.com // This if case is meant to capture what happens in a Broadcast/Snoop 2788532SLisa.Hsu@amd.com // protocol where the block does not exist in the cache hierarchy. You 2798532SLisa.Hsu@amd.com // only want to read from the Backing_Store memory if there is no copy in 2808532SLisa.Hsu@amd.com // the cache hierarchy, otherwise you want to try to read the RO or RW 2818532SLisa.Hsu@amd.com // copies existing in the cache hierarchy (covered by the else statement). 2828532SLisa.Hsu@amd.com // The reason is because the Backing_Store memory could easily be stale, if 2838532SLisa.Hsu@amd.com // there are copies floating around the cache hierarchy, so you want to read 2848532SLisa.Hsu@amd.com // it only if it's not in the cache hierarchy at all. 2858532SLisa.Hsu@amd.com if (num_invalid == (num_controllers - 1) && 2868532SLisa.Hsu@amd.com num_backing_store == 1) 2878436SBrad.Beckmann@amd.com { 2888532SLisa.Hsu@amd.com DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 2898532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 2908532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 2918532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 2928532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Backing_Store) { 2938532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 2948436SBrad.Beckmann@amd.com ->getDataBlock(line_address); 2958436SBrad.Beckmann@amd.com 2968532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 2978532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 2988532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 2998532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3008532SLisa.Hsu@amd.com } 3018532SLisa.Hsu@amd.com return true; 3028532SLisa.Hsu@amd.com } 3038532SLisa.Hsu@amd.com } 3048532SLisa.Hsu@amd.com } else { 3058532SLisa.Hsu@amd.com // In Broadcast/Snoop protocols, this covers if you know the block 3068532SLisa.Hsu@amd.com // exists somewhere in the caching hierarchy, then you want to read any 3078532SLisa.Hsu@amd.com // valid RO or RW block. In directory protocols, same thing, you want 3088532SLisa.Hsu@amd.com // to read any valid readable copy of the block. 3098532SLisa.Hsu@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3108532SLisa.Hsu@amd.com num_busy, num_ro, num_rw); 3118532SLisa.Hsu@amd.com // In this loop, we try to figure which controller has a read only or 3128532SLisa.Hsu@amd.com // a read write copy of the given address. Any valid copy would suffice 3138532SLisa.Hsu@amd.com // for a functional read. 3148532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3158532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3168532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3178532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3188532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write) 3198436SBrad.Beckmann@amd.com { 3208532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3218532SLisa.Hsu@amd.com ->getDataBlock(line_address); 3228532SLisa.Hsu@amd.com 3238532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3248532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3258532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3268532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3278532SLisa.Hsu@amd.com } 3288532SLisa.Hsu@amd.com return true; 3298436SBrad.Beckmann@amd.com } 3308436SBrad.Beckmann@amd.com } 3318436SBrad.Beckmann@amd.com } 3328436SBrad.Beckmann@amd.com return false; 3338436SBrad.Beckmann@amd.com} 3348436SBrad.Beckmann@amd.com 3358436SBrad.Beckmann@amd.combool 3368436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 3378436SBrad.Beckmann@amd.com{ 3388436SBrad.Beckmann@amd.com Address addr(pkt->getAddr()); 3398436SBrad.Beckmann@amd.com Address line_addr = line_address(addr); 3408532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 3418436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3428436SBrad.Beckmann@amd.com 3438436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 3448436SBrad.Beckmann@amd.com 3458436SBrad.Beckmann@amd.com unsigned int num_ro = 0; 3468436SBrad.Beckmann@amd.com unsigned int num_rw = 0; 3478436SBrad.Beckmann@amd.com unsigned int num_busy = 0; 3488532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 3498532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 3508436SBrad.Beckmann@amd.com 3518436SBrad.Beckmann@amd.com // In this loop we count the number of controllers that have the given 3528436SBrad.Beckmann@amd.com // address in read only, read write and busy states. 3538532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3548532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3558436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3568532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 3578532SLisa.Hsu@amd.com num_ro++; 3588532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 3598532SLisa.Hsu@amd.com num_rw++; 3608532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 3618532SLisa.Hsu@amd.com num_busy++; 3628532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 3638532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 3648532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 3658532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 3668532SLisa.Hsu@amd.com // or not. 3678532SLisa.Hsu@amd.com num_backing_store++; 3688532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 3698532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 3708532SLisa.Hsu@amd.com num_invalid++; 3718436SBrad.Beckmann@amd.com } 3728436SBrad.Beckmann@amd.com 3738436SBrad.Beckmann@amd.com // If the number of read write copies is more than 1, then there is bug in 3748436SBrad.Beckmann@amd.com // coherence protocol. Otherwise, if all copies are in stable states, i.e. 3758436SBrad.Beckmann@amd.com // num_busy == 0, we update all the copies. If there is at least one copy 3768436SBrad.Beckmann@amd.com // in busy state, then we check if there is read write copy. If yes, then 3778532SLisa.Hsu@amd.com // also we let the access go through. Or, if there is no copy in the cache 3788532SLisa.Hsu@amd.com // hierarchy at all, we still want to do the write to the memory 3798532SLisa.Hsu@amd.com // (Backing_Store) instead of failing. 3808436SBrad.Beckmann@amd.com 3818436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3828436SBrad.Beckmann@amd.com num_busy, num_ro, num_rw); 3838436SBrad.Beckmann@amd.com assert(num_rw <= 1); 3848532SLisa.Hsu@amd.com 3858532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3868532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 3878532SLisa.Hsu@amd.com unsigned startByte = addr.getAddress() - line_addr.getAddress(); 3888532SLisa.Hsu@amd.com 3898532SLisa.Hsu@amd.com if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 3908532SLisa.Hsu@amd.com (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 3918436SBrad.Beckmann@amd.com { 3928532SLisa.Hsu@amd.com for(int i = 0; i < num_controllers;++i) { 3938532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3948436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3958532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3968532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write|| 3978532SLisa.Hsu@amd.com access_perm == AccessPermission_Maybe_Stale || 3988532SLisa.Hsu@amd.com access_perm == AccessPermission_Backing_Store) 3998436SBrad.Beckmann@amd.com { 4008436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 4018436SBrad.Beckmann@amd.com ->getDataBlock(line_addr); 4028436SBrad.Beckmann@amd.com 4038436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4048532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 4058436SBrad.Beckmann@amd.com block.setByte(i + startByte, data[i]); 4068436SBrad.Beckmann@amd.com } 4078436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4088436SBrad.Beckmann@amd.com } 4098436SBrad.Beckmann@amd.com } 4108436SBrad.Beckmann@amd.com return true; 4118436SBrad.Beckmann@amd.com } 4128436SBrad.Beckmann@amd.com return false; 4138436SBrad.Beckmann@amd.com} 4148436SBrad.Beckmann@amd.com 4158436SBrad.Beckmann@amd.comvoid 4168436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 4178436SBrad.Beckmann@amd.com{ 4188436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 4198436SBrad.Beckmann@amd.com pkt->getAddr()); 4208436SBrad.Beckmann@amd.com 4218436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 4228436SBrad.Beckmann@amd.com // pio port. 4238436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 4248436SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 4258436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 4268436SBrad.Beckmann@amd.com pkt->getAddr()); 4278436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 4288436SBrad.Beckmann@amd.com } 4298436SBrad.Beckmann@amd.com 4308436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 4318436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 4328436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 4338436SBrad.Beckmann@amd.com 4348436SBrad.Beckmann@amd.com bool accessSucceeded = false; 4358436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4368436SBrad.Beckmann@amd.com 4378436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 4388436SBrad.Beckmann@amd.com if (pkt->isRead()) { 4398436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalRead(pkt); 4408436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 4418436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalWrite(pkt); 4428436SBrad.Beckmann@amd.com } else { 4438436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 4448436SBrad.Beckmann@amd.com pkt->cmdString()); 4458436SBrad.Beckmann@amd.com } 4468436SBrad.Beckmann@amd.com 4478436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 4488436SBrad.Beckmann@amd.com // the functional request failed 4498436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 4508436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 4518436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 4528436SBrad.Beckmann@amd.com } 4538436SBrad.Beckmann@amd.com 4548436SBrad.Beckmann@amd.com if (access_phys_mem) { 4558436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 4568436SBrad.Beckmann@amd.com // The following command performs the real functional access. 4578436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 4588436SBrad.Beckmann@amd.com // of data. 4598436SBrad.Beckmann@amd.com ruby_port->physMemPort->sendFunctional(pkt); 4608436SBrad.Beckmann@amd.com } 4618436SBrad.Beckmann@amd.com 4628436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4638436SBrad.Beckmann@amd.com if (needsResponse) { 4648436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 4658436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4668436SBrad.Beckmann@amd.com sendFunctional(pkt); 4678436SBrad.Beckmann@amd.com } 4688436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 4698436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 4708436SBrad.Beckmann@amd.com} 4718436SBrad.Beckmann@amd.com 4726882SBrad.Beckmann@amd.comvoid 4736922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 4746882SBrad.Beckmann@amd.com{ 4756922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 4767039Snate@binkert.org RubyPort::SenderState *senderState = 4776922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 4786922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 4796922SBrad.Beckmann@amd.com assert(port != NULL); 4807039Snate@binkert.org 4816922SBrad.Beckmann@amd.com // pop the sender state from the packet 4826922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 4836922SBrad.Beckmann@amd.com delete senderState; 4846882SBrad.Beckmann@amd.com 4856882SBrad.Beckmann@amd.com port->hitCallback(pkt); 4867910SBrad.Beckmann@amd.com 4877910SBrad.Beckmann@amd.com // 4887910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 4897910SBrad.Beckmann@amd.com // likely has free resources now. 4907910SBrad.Beckmann@amd.com // 4917910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 4928162SBrad.Beckmann@amd.com // 4938162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 4948162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 4958162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 4968162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 4978162SBrad.Beckmann@amd.com // sendRetry. 4988162SBrad.Beckmann@amd.com // 4998162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 5008162SBrad.Beckmann@amd.com 5018162SBrad.Beckmann@amd.com retryList.clear(); 5028162SBrad.Beckmann@amd.com waitingOnSequencer = false; 5038162SBrad.Beckmann@amd.com 5048162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 5058162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 5068162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 5077910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 5087910SBrad.Beckmann@amd.com (*i)->name()); 5098162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 5108162SBrad.Beckmann@amd.com (*i)->sendRetry(); 5117910SBrad.Beckmann@amd.com } 5127910SBrad.Beckmann@amd.com } 5136882SBrad.Beckmann@amd.com} 5146882SBrad.Beckmann@amd.com 5156882SBrad.Beckmann@amd.comvoid 5166882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 5176882SBrad.Beckmann@amd.com{ 5186882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 5196882SBrad.Beckmann@amd.com 5207550SBrad.Beckmann@amd.com // 5217915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 5228184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 5237550SBrad.Beckmann@amd.com // 5247915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 5257550SBrad.Beckmann@amd.com 5267550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 5277550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 5287550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 5297550SBrad.Beckmann@amd.com // 5307550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 5317550SBrad.Beckmann@amd.com // 5327550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 5337550SBrad.Beckmann@amd.com } else { 5347550SBrad.Beckmann@amd.com // 5357550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 5367550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 5377550SBrad.Beckmann@amd.com // 5387550SBrad.Beckmann@amd.com accessPhysMem = false; 5397550SBrad.Beckmann@amd.com } 5407550SBrad.Beckmann@amd.com } else { 5417550SBrad.Beckmann@amd.com // 5427550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 5437550SBrad.Beckmann@amd.com // not lock the blocks. 5447550SBrad.Beckmann@amd.com // 5457550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 5467550SBrad.Beckmann@amd.com } 5477550SBrad.Beckmann@amd.com } 5488184Ssomayeh@cs.wisc.edu 5498184Ssomayeh@cs.wisc.edu // 5508184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 5518184Ssomayeh@cs.wisc.edu // 5528184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 5538184Ssomayeh@cs.wisc.edu accessPhysMem = false; 5548184Ssomayeh@cs.wisc.edu } 5558184Ssomayeh@cs.wisc.edu 5568161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 5576882SBrad.Beckmann@amd.com 5587550SBrad.Beckmann@amd.com if (accessPhysMem) { 5597550SBrad.Beckmann@amd.com ruby_port->physMemPort->sendAtomic(pkt); 5608184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 5617915SBrad.Beckmann@amd.com pkt->makeResponse(); 5627550SBrad.Beckmann@amd.com } 5636882SBrad.Beckmann@amd.com 5646882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 5656882SBrad.Beckmann@amd.com if (needsResponse) { 5668161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 5676882SBrad.Beckmann@amd.com sendTiming(pkt); 5686882SBrad.Beckmann@amd.com } else { 5696882SBrad.Beckmann@amd.com delete pkt; 5706882SBrad.Beckmann@amd.com } 5718161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 5726882SBrad.Beckmann@amd.com} 5736882SBrad.Beckmann@amd.com 5746882SBrad.Beckmann@amd.combool 5756882SBrad.Beckmann@amd.comRubyPort::M5Port::sendTiming(PacketPtr pkt) 5766882SBrad.Beckmann@amd.com{ 5777558SBrad.Beckmann@amd.com //minimum latency, must be > 0 5787823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 5796882SBrad.Beckmann@amd.com return true; 5806882SBrad.Beckmann@amd.com} 5816882SBrad.Beckmann@amd.com 5826882SBrad.Beckmann@amd.combool 5836882SBrad.Beckmann@amd.comRubyPort::PioPort::sendTiming(PacketPtr pkt) 5846882SBrad.Beckmann@amd.com{ 5857558SBrad.Beckmann@amd.com //minimum latency, must be > 0 5867823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 5876882SBrad.Beckmann@amd.com return true; 5886882SBrad.Beckmann@amd.com} 5896882SBrad.Beckmann@amd.com 5906882SBrad.Beckmann@amd.combool 5916882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 5926882SBrad.Beckmann@amd.com{ 5936882SBrad.Beckmann@amd.com AddrRangeList physMemAddrList; 5946882SBrad.Beckmann@amd.com bool snoop = false; 5956893SBrad.Beckmann@amd.com ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop); 5967039Snate@binkert.org for (AddrRangeIter iter = physMemAddrList.begin(); 5977039Snate@binkert.org iter != physMemAddrList.end(); 5987039Snate@binkert.org iter++) { 5996882SBrad.Beckmann@amd.com if (addr >= iter->start && addr <= iter->end) { 6008161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 6016882SBrad.Beckmann@amd.com iter->start, iter->end); 6026882SBrad.Beckmann@amd.com return true; 6036882SBrad.Beckmann@amd.com } 6046882SBrad.Beckmann@amd.com } 6056882SBrad.Beckmann@amd.com return false; 6066882SBrad.Beckmann@amd.com} 6077909Shestness@cs.utexas.edu 6087909Shestness@cs.utexas.eduunsigned 6097909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 6107909Shestness@cs.utexas.edu{ 6117909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 6127909Shestness@cs.utexas.edu} 613