RubyPort.cc revision 8532
16876Ssteve.reinhardt@amd.com/* 26876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 36876Ssteve.reinhardt@amd.com * All rights reserved. 46876Ssteve.reinhardt@amd.com * 56876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 66876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 76876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 86876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 96876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 106876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 126876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 136876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 146876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 156876Ssteve.reinhardt@amd.com * 166876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276876Ssteve.reinhardt@amd.com */ 286876Ssteve.reinhardt@amd.com 297908Shestness@cs.utexas.edu#include "config/the_isa.hh" 307908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 317908Shestness@cs.utexas.edu#include "arch/x86/insts/microldstop.hh" 327908Shestness@cs.utexas.edu#endif // X86_ISA 337632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 348232Snate@binkert.org#include "debug/Ruby.hh" 358436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 367039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 376285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 388229Snate@binkert.org#include "mem/physical.hh" 396285Snate@binkert.org 406876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 416893SBrad.Beckmann@amd.com : MemObject(p) 426876Ssteve.reinhardt@amd.com{ 436876Ssteve.reinhardt@amd.com m_version = p->version; 446876Ssteve.reinhardt@amd.com assert(m_version != -1); 456876Ssteve.reinhardt@amd.com 466893SBrad.Beckmann@amd.com physmem = p->physmem; 477039Snate@binkert.org 486882SBrad.Beckmann@amd.com m_controller = NULL; 496882SBrad.Beckmann@amd.com m_mandatory_q_ptr = NULL; 506876Ssteve.reinhardt@amd.com 516876Ssteve.reinhardt@amd.com m_request_cnt = 0; 526882SBrad.Beckmann@amd.com pio_port = NULL; 536893SBrad.Beckmann@amd.com physMemPort = NULL; 547910SBrad.Beckmann@amd.com 557910SBrad.Beckmann@amd.com m_usingRubyTester = p->using_ruby_tester; 567915SBrad.Beckmann@amd.com access_phys_mem = p->access_phys_mem; 578436SBrad.Beckmann@amd.com 588436SBrad.Beckmann@amd.com ruby_system = p->ruby_system; 598505Snilay@cs.wisc.edu waitingOnSequencer = false; 606876Ssteve.reinhardt@amd.com} 616876Ssteve.reinhardt@amd.com 627039Snate@binkert.orgvoid 637039Snate@binkert.orgRubyPort::init() 646882SBrad.Beckmann@amd.com{ 656882SBrad.Beckmann@amd.com assert(m_controller != NULL); 666882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 676882SBrad.Beckmann@amd.com} 686882SBrad.Beckmann@amd.com 696876Ssteve.reinhardt@amd.comPort * 706876Ssteve.reinhardt@amd.comRubyPort::getPort(const std::string &if_name, int idx) 716876Ssteve.reinhardt@amd.com{ 726882SBrad.Beckmann@amd.com if (if_name == "port") { 737915SBrad.Beckmann@amd.com return new M5Port(csprintf("%s-port%d", name(), idx), this, 748436SBrad.Beckmann@amd.com ruby_system, access_phys_mem); 757039Snate@binkert.org } 767039Snate@binkert.org 777039Snate@binkert.org if (if_name == "pio_port") { 786882SBrad.Beckmann@amd.com // ensure there is only one pio port 796882SBrad.Beckmann@amd.com assert(pio_port == NULL); 806882SBrad.Beckmann@amd.com 817039Snate@binkert.org pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this); 826882SBrad.Beckmann@amd.com 836882SBrad.Beckmann@amd.com return pio_port; 847039Snate@binkert.org } 857039Snate@binkert.org 867039Snate@binkert.org if (if_name == "physMemPort") { 876893SBrad.Beckmann@amd.com // RubyPort should only have one port to physical memory 886893SBrad.Beckmann@amd.com assert (physMemPort == NULL); 896893SBrad.Beckmann@amd.com 907915SBrad.Beckmann@amd.com physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, 918436SBrad.Beckmann@amd.com ruby_system, access_phys_mem); 927039Snate@binkert.org 936893SBrad.Beckmann@amd.com return physMemPort; 947039Snate@binkert.org } 957039Snate@binkert.org 967039Snate@binkert.org if (if_name == "functional") { 977039Snate@binkert.org // Calls for the functional port only want to access 987039Snate@binkert.org // functional memory. Therefore, directly pass these calls 997039Snate@binkert.org // ports to physmem. 1006893SBrad.Beckmann@amd.com assert(physmem != NULL); 1016893SBrad.Beckmann@amd.com return physmem->getPort(if_name, idx); 1026882SBrad.Beckmann@amd.com } 1037039Snate@binkert.org 1046876Ssteve.reinhardt@amd.com return NULL; 1056876Ssteve.reinhardt@amd.com} 1066882SBrad.Beckmann@amd.com 1077039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1086882SBrad.Beckmann@amd.com RubyPort *_port) 1096882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1106882SBrad.Beckmann@amd.com{ 1118161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name); 1126882SBrad.Beckmann@amd.com ruby_port = _port; 1136882SBrad.Beckmann@amd.com} 1146882SBrad.Beckmann@amd.com 1158436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1168436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1176882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1186882SBrad.Beckmann@amd.com{ 1198161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name); 1206882SBrad.Beckmann@amd.com ruby_port = _port; 1218436SBrad.Beckmann@amd.com ruby_system = _system; 1227910SBrad.Beckmann@amd.com _onRetryList = false; 1237915SBrad.Beckmann@amd.com access_phys_mem = _access_phys_mem; 1246882SBrad.Beckmann@amd.com} 1256882SBrad.Beckmann@amd.com 1266882SBrad.Beckmann@amd.comTick 1276882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1286882SBrad.Beckmann@amd.com{ 1296882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1306882SBrad.Beckmann@amd.com return 0; 1316882SBrad.Beckmann@amd.com} 1326882SBrad.Beckmann@amd.com 1336882SBrad.Beckmann@amd.comTick 1346882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1356882SBrad.Beckmann@amd.com{ 1366882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1376882SBrad.Beckmann@amd.com return 0; 1386882SBrad.Beckmann@amd.com} 1396882SBrad.Beckmann@amd.com 1406882SBrad.Beckmann@amd.com 1416882SBrad.Beckmann@amd.combool 1426882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1436882SBrad.Beckmann@amd.com{ 1447039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1457039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1468161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1476882SBrad.Beckmann@amd.com 1486882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1496882SBrad.Beckmann@amd.com 1506882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1517039Snate@binkert.org RubyPort::SenderState *senderState = 1526882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1536882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1546882SBrad.Beckmann@amd.com assert(port != NULL); 1557039Snate@binkert.org 1566882SBrad.Beckmann@amd.com // pop the sender state from the packet 1576882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1586882SBrad.Beckmann@amd.com delete senderState; 1597039Snate@binkert.org 1606882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1617039Snate@binkert.org 1626882SBrad.Beckmann@amd.com return true; 1636882SBrad.Beckmann@amd.com} 1646882SBrad.Beckmann@amd.com 1656882SBrad.Beckmann@amd.combool 1666882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1676882SBrad.Beckmann@amd.com{ 1688161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1697039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1706882SBrad.Beckmann@amd.com 1716882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1726882SBrad.Beckmann@amd.com 1737039Snate@binkert.org // The received packets should only be M5 requests, which should never 1747039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1757039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1766882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1776882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1786882SBrad.Beckmann@amd.com 1796882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1806882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1816882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1826882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1836882SBrad.Beckmann@amd.com delete pkt; 1846882SBrad.Beckmann@amd.com return true; 1856882SBrad.Beckmann@amd.com } 1866882SBrad.Beckmann@amd.com 1876922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1886922SBrad.Beckmann@amd.com // route the response 1896922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1906922SBrad.Beckmann@amd.com 1916882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1926882SBrad.Beckmann@amd.com // pio port. 1936882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1946882SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 1958161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1966922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1976922SBrad.Beckmann@amd.com pkt->getAddr()); 1986882SBrad.Beckmann@amd.com 1996882SBrad.Beckmann@amd.com return ruby_port->pio_port->sendTiming(pkt); 2006882SBrad.Beckmann@amd.com } 2016882SBrad.Beckmann@amd.com 2026882SBrad.Beckmann@amd.com // For DMA and CPU requests, translate them to ruby requests before 2036882SBrad.Beckmann@amd.com // sending them to our assigned ruby port. 2046882SBrad.Beckmann@amd.com RubyRequestType type = RubyRequestType_NULL; 2056899SBrad.Beckmann@amd.com 2066899SBrad.Beckmann@amd.com // If valid, copy the pc to the ruby request 2076882SBrad.Beckmann@amd.com Addr pc = 0; 2086899SBrad.Beckmann@amd.com if (pkt->req->hasPC()) { 2096899SBrad.Beckmann@amd.com pc = pkt->req->getPC(); 2106899SBrad.Beckmann@amd.com } 2116899SBrad.Beckmann@amd.com 2127023SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 2137023SBrad.Beckmann@amd.com if (pkt->isWrite()) { 2148161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing SC\n"); 2157907Shestness@cs.utexas.edu type = RubyRequestType_Store_Conditional; 2166882SBrad.Beckmann@amd.com } else { 2178161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing LL\n"); 2187023SBrad.Beckmann@amd.com assert(pkt->isRead()); 2197907Shestness@cs.utexas.edu type = RubyRequestType_Load_Linked; 2206882SBrad.Beckmann@amd.com } 2217908Shestness@cs.utexas.edu } else if (pkt->req->isLocked()) { 2227908Shestness@cs.utexas.edu if (pkt->isWrite()) { 2238161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Write\n"); 2247908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Write; 2257908Shestness@cs.utexas.edu } else { 2268161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Read\n"); 2277908Shestness@cs.utexas.edu assert(pkt->isRead()); 2287908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Read; 2297908Shestness@cs.utexas.edu } 2306922SBrad.Beckmann@amd.com } else { 2317023SBrad.Beckmann@amd.com if (pkt->isRead()) { 2327023SBrad.Beckmann@amd.com if (pkt->req->isInstFetch()) { 2337023SBrad.Beckmann@amd.com type = RubyRequestType_IFETCH; 2347023SBrad.Beckmann@amd.com } else { 2357908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 2367908Shestness@cs.utexas.edu uint32_t flags = pkt->req->getFlags(); 2377908Shestness@cs.utexas.edu bool storeCheck = flags & 2387908Shestness@cs.utexas.edu (TheISA::StoreCheck << TheISA::FlagShift); 2397908Shestness@cs.utexas.edu#else 2407908Shestness@cs.utexas.edu bool storeCheck = false; 2417908Shestness@cs.utexas.edu#endif // X86_ISA 2427908Shestness@cs.utexas.edu if (storeCheck) { 2437908Shestness@cs.utexas.edu type = RubyRequestType_RMW_Read; 2447908Shestness@cs.utexas.edu } else { 2457908Shestness@cs.utexas.edu type = RubyRequestType_LD; 2467908Shestness@cs.utexas.edu } 2477023SBrad.Beckmann@amd.com } 2487023SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2497908Shestness@cs.utexas.edu // 2507908Shestness@cs.utexas.edu // Note: M5 packets do not differentiate ST from RMW_Write 2517908Shestness@cs.utexas.edu // 2527023SBrad.Beckmann@amd.com type = RubyRequestType_ST; 2538184Ssomayeh@cs.wisc.edu } else if (pkt->isFlush()) { 2548184Ssomayeh@cs.wisc.edu type = RubyRequestType_FLUSH; 2557023SBrad.Beckmann@amd.com } else { 2567023SBrad.Beckmann@amd.com panic("Unsupported ruby packet type\n"); 2577023SBrad.Beckmann@amd.com } 2586882SBrad.Beckmann@amd.com } 2596882SBrad.Beckmann@amd.com 2607915SBrad.Beckmann@amd.com RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true), 2617039Snate@binkert.org pkt->getSize(), pc, type, 2627039Snate@binkert.org RubyAccessMode_Supervisor, pkt); 2636882SBrad.Beckmann@amd.com 2648174Snilay@cs.wisc.edu assert(ruby_request.m_PhysicalAddress.getOffset() + ruby_request.m_Size <= 2657906SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2667906SBrad.Beckmann@amd.com 2676882SBrad.Beckmann@amd.com // Submit the ruby request 2686922SBrad.Beckmann@amd.com RequestStatus requestStatus = ruby_port->makeRequest(ruby_request); 2697023SBrad.Beckmann@amd.com 2707550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2717023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2727023SBrad.Beckmann@amd.com // false. 2737550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2748161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2756922SBrad.Beckmann@amd.com return true; 2766882SBrad.Beckmann@amd.com } 2777023SBrad.Beckmann@amd.com 2787910SBrad.Beckmann@amd.com // 2797910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2807910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2817910SBrad.Beckmann@amd.com // 2827910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2837910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2847910SBrad.Beckmann@amd.com } 2857910SBrad.Beckmann@amd.com 2868161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2877906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2887039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2897039Snate@binkert.org 2906922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2916922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2926922SBrad.Beckmann@amd.com delete senderState; 2936922SBrad.Beckmann@amd.com return false; 2946882SBrad.Beckmann@amd.com} 2956882SBrad.Beckmann@amd.com 2968436SBrad.Beckmann@amd.combool 2978436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 2988436SBrad.Beckmann@amd.com{ 2998436SBrad.Beckmann@amd.com Address address(pkt->getAddr()); 3008436SBrad.Beckmann@amd.com Address line_address(address); 3018436SBrad.Beckmann@amd.com line_address.makeLineAddress(); 3028436SBrad.Beckmann@amd.com 3038532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 3048436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3058436SBrad.Beckmann@amd.com 3068532SLisa.Hsu@amd.com DPRINTF(RubyPort, "Functional Read request for %s\n",address); 3078436SBrad.Beckmann@amd.com 3088532SLisa.Hsu@amd.com unsigned int num_ro = 0; 3098532SLisa.Hsu@amd.com unsigned int num_rw = 0; 3108532SLisa.Hsu@amd.com unsigned int num_busy = 0; 3118532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 3128532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 3138532SLisa.Hsu@amd.com 3148532SLisa.Hsu@amd.com // In this loop we count the number of controllers that have the given 3158532SLisa.Hsu@amd.com // address in read only, read write and busy states. 3168532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 3178532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3188532SLisa.Hsu@amd.com getAccessPermission(line_address); 3198532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 3208532SLisa.Hsu@amd.com num_ro++; 3218532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 3228532SLisa.Hsu@amd.com num_rw++; 3238532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 3248532SLisa.Hsu@amd.com num_busy++; 3258532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 3268532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 3278532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 3288532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 3298532SLisa.Hsu@amd.com // or not. 3308532SLisa.Hsu@amd.com num_backing_store++; 3318532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 3328532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 3338532SLisa.Hsu@amd.com num_invalid++; 3348532SLisa.Hsu@amd.com } 3358532SLisa.Hsu@amd.com assert(num_rw <= 1); 3368532SLisa.Hsu@amd.com 3378532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3388532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 3398532SLisa.Hsu@amd.com unsigned startByte = address.getAddress() - line_address.getAddress(); 3408532SLisa.Hsu@amd.com 3418532SLisa.Hsu@amd.com // This if case is meant to capture what happens in a Broadcast/Snoop 3428532SLisa.Hsu@amd.com // protocol where the block does not exist in the cache hierarchy. You 3438532SLisa.Hsu@amd.com // only want to read from the Backing_Store memory if there is no copy in 3448532SLisa.Hsu@amd.com // the cache hierarchy, otherwise you want to try to read the RO or RW 3458532SLisa.Hsu@amd.com // copies existing in the cache hierarchy (covered by the else statement). 3468532SLisa.Hsu@amd.com // The reason is because the Backing_Store memory could easily be stale, if 3478532SLisa.Hsu@amd.com // there are copies floating around the cache hierarchy, so you want to read 3488532SLisa.Hsu@amd.com // it only if it's not in the cache hierarchy at all. 3498532SLisa.Hsu@amd.com if (num_invalid == (num_controllers - 1) && 3508532SLisa.Hsu@amd.com num_backing_store == 1) 3518436SBrad.Beckmann@amd.com { 3528532SLisa.Hsu@amd.com DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 3538532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 3548532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3558532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3568532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Backing_Store) { 3578532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3588436SBrad.Beckmann@amd.com ->getDataBlock(line_address); 3598436SBrad.Beckmann@amd.com 3608532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3618532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3628532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3638532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3648532SLisa.Hsu@amd.com } 3658532SLisa.Hsu@amd.com return true; 3668532SLisa.Hsu@amd.com } 3678532SLisa.Hsu@amd.com } 3688532SLisa.Hsu@amd.com } else { 3698532SLisa.Hsu@amd.com // In Broadcast/Snoop protocols, this covers if you know the block 3708532SLisa.Hsu@amd.com // exists somewhere in the caching hierarchy, then you want to read any 3718532SLisa.Hsu@amd.com // valid RO or RW block. In directory protocols, same thing, you want 3728532SLisa.Hsu@amd.com // to read any valid readable copy of the block. 3738532SLisa.Hsu@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3748532SLisa.Hsu@amd.com num_busy, num_ro, num_rw); 3758532SLisa.Hsu@amd.com // In this loop, we try to figure which controller has a read only or 3768532SLisa.Hsu@amd.com // a read write copy of the given address. Any valid copy would suffice 3778532SLisa.Hsu@amd.com // for a functional read. 3788532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3798532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3808532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3818532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3828532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write) 3838436SBrad.Beckmann@amd.com { 3848532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3858532SLisa.Hsu@amd.com ->getDataBlock(line_address); 3868532SLisa.Hsu@amd.com 3878532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3888532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3898532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3908532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3918532SLisa.Hsu@amd.com } 3928532SLisa.Hsu@amd.com return true; 3938436SBrad.Beckmann@amd.com } 3948436SBrad.Beckmann@amd.com } 3958436SBrad.Beckmann@amd.com } 3968436SBrad.Beckmann@amd.com return false; 3978436SBrad.Beckmann@amd.com} 3988436SBrad.Beckmann@amd.com 3998436SBrad.Beckmann@amd.combool 4008436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 4018436SBrad.Beckmann@amd.com{ 4028436SBrad.Beckmann@amd.com Address addr(pkt->getAddr()); 4038436SBrad.Beckmann@amd.com Address line_addr = line_address(addr); 4048532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 4058436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 4068436SBrad.Beckmann@amd.com 4078436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 4088436SBrad.Beckmann@amd.com 4098436SBrad.Beckmann@amd.com unsigned int num_ro = 0; 4108436SBrad.Beckmann@amd.com unsigned int num_rw = 0; 4118436SBrad.Beckmann@amd.com unsigned int num_busy = 0; 4128532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 4138532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 4148436SBrad.Beckmann@amd.com 4158436SBrad.Beckmann@amd.com // In this loop we count the number of controllers that have the given 4168436SBrad.Beckmann@amd.com // address in read only, read write and busy states. 4178532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 4188532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 4198436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 4208532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 4218532SLisa.Hsu@amd.com num_ro++; 4228532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 4238532SLisa.Hsu@amd.com num_rw++; 4248532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 4258532SLisa.Hsu@amd.com num_busy++; 4268532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 4278532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 4288532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 4298532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 4308532SLisa.Hsu@amd.com // or not. 4318532SLisa.Hsu@amd.com num_backing_store++; 4328532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 4338532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 4348532SLisa.Hsu@amd.com num_invalid++; 4358436SBrad.Beckmann@amd.com } 4368436SBrad.Beckmann@amd.com 4378436SBrad.Beckmann@amd.com // If the number of read write copies is more than 1, then there is bug in 4388436SBrad.Beckmann@amd.com // coherence protocol. Otherwise, if all copies are in stable states, i.e. 4398436SBrad.Beckmann@amd.com // num_busy == 0, we update all the copies. If there is at least one copy 4408436SBrad.Beckmann@amd.com // in busy state, then we check if there is read write copy. If yes, then 4418532SLisa.Hsu@amd.com // also we let the access go through. Or, if there is no copy in the cache 4428532SLisa.Hsu@amd.com // hierarchy at all, we still want to do the write to the memory 4438532SLisa.Hsu@amd.com // (Backing_Store) instead of failing. 4448436SBrad.Beckmann@amd.com 4458436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 4468436SBrad.Beckmann@amd.com num_busy, num_ro, num_rw); 4478436SBrad.Beckmann@amd.com assert(num_rw <= 1); 4488532SLisa.Hsu@amd.com 4498532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 4508532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 4518532SLisa.Hsu@amd.com unsigned startByte = addr.getAddress() - line_addr.getAddress(); 4528532SLisa.Hsu@amd.com 4538532SLisa.Hsu@amd.com if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 4548532SLisa.Hsu@amd.com (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 4558436SBrad.Beckmann@amd.com { 4568532SLisa.Hsu@amd.com for(int i = 0; i < num_controllers;++i) { 4578532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 4588436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 4598532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 4608532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write|| 4618532SLisa.Hsu@amd.com access_perm == AccessPermission_Maybe_Stale || 4628532SLisa.Hsu@amd.com access_perm == AccessPermission_Backing_Store) 4638436SBrad.Beckmann@amd.com { 4648436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 4658436SBrad.Beckmann@amd.com ->getDataBlock(line_addr); 4668436SBrad.Beckmann@amd.com 4678436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4688532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 4698436SBrad.Beckmann@amd.com block.setByte(i + startByte, data[i]); 4708436SBrad.Beckmann@amd.com } 4718436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4728436SBrad.Beckmann@amd.com } 4738436SBrad.Beckmann@amd.com } 4748436SBrad.Beckmann@amd.com return true; 4758436SBrad.Beckmann@amd.com } 4768436SBrad.Beckmann@amd.com return false; 4778436SBrad.Beckmann@amd.com} 4788436SBrad.Beckmann@amd.com 4798436SBrad.Beckmann@amd.comvoid 4808436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 4818436SBrad.Beckmann@amd.com{ 4828436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 4838436SBrad.Beckmann@amd.com pkt->getAddr()); 4848436SBrad.Beckmann@amd.com 4858436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 4868436SBrad.Beckmann@amd.com // pio port. 4878436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 4888436SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 4898436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 4908436SBrad.Beckmann@amd.com pkt->getAddr()); 4918436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 4928436SBrad.Beckmann@amd.com } 4938436SBrad.Beckmann@amd.com 4948436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 4958436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 4968436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 4978436SBrad.Beckmann@amd.com 4988436SBrad.Beckmann@amd.com bool accessSucceeded = false; 4998436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 5008436SBrad.Beckmann@amd.com 5018436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 5028436SBrad.Beckmann@amd.com if (pkt->isRead()) { 5038436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalRead(pkt); 5048436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 5058436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalWrite(pkt); 5068436SBrad.Beckmann@amd.com } else { 5078436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 5088436SBrad.Beckmann@amd.com pkt->cmdString()); 5098436SBrad.Beckmann@amd.com } 5108436SBrad.Beckmann@amd.com 5118436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 5128436SBrad.Beckmann@amd.com // the functional request failed 5138436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 5148436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 5158436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 5168436SBrad.Beckmann@amd.com } 5178436SBrad.Beckmann@amd.com 5188436SBrad.Beckmann@amd.com if (access_phys_mem) { 5198436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 5208436SBrad.Beckmann@amd.com // The following command performs the real functional access. 5218436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 5228436SBrad.Beckmann@amd.com // of data. 5238436SBrad.Beckmann@amd.com ruby_port->physMemPort->sendFunctional(pkt); 5248436SBrad.Beckmann@amd.com } 5258436SBrad.Beckmann@amd.com 5268436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 5278436SBrad.Beckmann@amd.com if (needsResponse) { 5288436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 5298436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 5308436SBrad.Beckmann@amd.com sendFunctional(pkt); 5318436SBrad.Beckmann@amd.com } 5328436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 5338436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 5348436SBrad.Beckmann@amd.com} 5358436SBrad.Beckmann@amd.com 5366882SBrad.Beckmann@amd.comvoid 5376922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 5386882SBrad.Beckmann@amd.com{ 5396922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 5407039Snate@binkert.org RubyPort::SenderState *senderState = 5416922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 5426922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 5436922SBrad.Beckmann@amd.com assert(port != NULL); 5447039Snate@binkert.org 5456922SBrad.Beckmann@amd.com // pop the sender state from the packet 5466922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 5476922SBrad.Beckmann@amd.com delete senderState; 5486882SBrad.Beckmann@amd.com 5496882SBrad.Beckmann@amd.com port->hitCallback(pkt); 5507910SBrad.Beckmann@amd.com 5517910SBrad.Beckmann@amd.com // 5527910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 5537910SBrad.Beckmann@amd.com // likely has free resources now. 5547910SBrad.Beckmann@amd.com // 5557910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 5568162SBrad.Beckmann@amd.com // 5578162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 5588162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 5598162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 5608162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 5618162SBrad.Beckmann@amd.com // sendRetry. 5628162SBrad.Beckmann@amd.com // 5638162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 5648162SBrad.Beckmann@amd.com 5658162SBrad.Beckmann@amd.com retryList.clear(); 5668162SBrad.Beckmann@amd.com waitingOnSequencer = false; 5678162SBrad.Beckmann@amd.com 5688162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 5698162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 5708162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 5717910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 5727910SBrad.Beckmann@amd.com (*i)->name()); 5738162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 5748162SBrad.Beckmann@amd.com (*i)->sendRetry(); 5757910SBrad.Beckmann@amd.com } 5767910SBrad.Beckmann@amd.com } 5776882SBrad.Beckmann@amd.com} 5786882SBrad.Beckmann@amd.com 5796882SBrad.Beckmann@amd.comvoid 5806882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 5816882SBrad.Beckmann@amd.com{ 5826882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 5836882SBrad.Beckmann@amd.com 5847550SBrad.Beckmann@amd.com // 5857915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 5868184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 5877550SBrad.Beckmann@amd.com // 5887915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 5897550SBrad.Beckmann@amd.com 5907550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 5917550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 5927550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 5937550SBrad.Beckmann@amd.com // 5947550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 5957550SBrad.Beckmann@amd.com // 5967550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 5977550SBrad.Beckmann@amd.com } else { 5987550SBrad.Beckmann@amd.com // 5997550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 6007550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 6017550SBrad.Beckmann@amd.com // 6027550SBrad.Beckmann@amd.com accessPhysMem = false; 6037550SBrad.Beckmann@amd.com } 6047550SBrad.Beckmann@amd.com } else { 6057550SBrad.Beckmann@amd.com // 6067550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 6077550SBrad.Beckmann@amd.com // not lock the blocks. 6087550SBrad.Beckmann@amd.com // 6097550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 6107550SBrad.Beckmann@amd.com } 6117550SBrad.Beckmann@amd.com } 6128184Ssomayeh@cs.wisc.edu 6138184Ssomayeh@cs.wisc.edu // 6148184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 6158184Ssomayeh@cs.wisc.edu // 6168184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 6178184Ssomayeh@cs.wisc.edu accessPhysMem = false; 6188184Ssomayeh@cs.wisc.edu } 6198184Ssomayeh@cs.wisc.edu 6208161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 6216882SBrad.Beckmann@amd.com 6227550SBrad.Beckmann@amd.com if (accessPhysMem) { 6237550SBrad.Beckmann@amd.com ruby_port->physMemPort->sendAtomic(pkt); 6248184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 6257915SBrad.Beckmann@amd.com pkt->makeResponse(); 6267550SBrad.Beckmann@amd.com } 6276882SBrad.Beckmann@amd.com 6286882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 6296882SBrad.Beckmann@amd.com if (needsResponse) { 6308161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 6316882SBrad.Beckmann@amd.com sendTiming(pkt); 6326882SBrad.Beckmann@amd.com } else { 6336882SBrad.Beckmann@amd.com delete pkt; 6346882SBrad.Beckmann@amd.com } 6358161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 6366882SBrad.Beckmann@amd.com} 6376882SBrad.Beckmann@amd.com 6386882SBrad.Beckmann@amd.combool 6396882SBrad.Beckmann@amd.comRubyPort::M5Port::sendTiming(PacketPtr pkt) 6406882SBrad.Beckmann@amd.com{ 6417558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6427823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6436882SBrad.Beckmann@amd.com return true; 6446882SBrad.Beckmann@amd.com} 6456882SBrad.Beckmann@amd.com 6466882SBrad.Beckmann@amd.combool 6476882SBrad.Beckmann@amd.comRubyPort::PioPort::sendTiming(PacketPtr pkt) 6486882SBrad.Beckmann@amd.com{ 6497558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6507823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6516882SBrad.Beckmann@amd.com return true; 6526882SBrad.Beckmann@amd.com} 6536882SBrad.Beckmann@amd.com 6546882SBrad.Beckmann@amd.combool 6556882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 6566882SBrad.Beckmann@amd.com{ 6576882SBrad.Beckmann@amd.com AddrRangeList physMemAddrList; 6586882SBrad.Beckmann@amd.com bool snoop = false; 6596893SBrad.Beckmann@amd.com ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop); 6607039Snate@binkert.org for (AddrRangeIter iter = physMemAddrList.begin(); 6617039Snate@binkert.org iter != physMemAddrList.end(); 6627039Snate@binkert.org iter++) { 6636882SBrad.Beckmann@amd.com if (addr >= iter->start && addr <= iter->end) { 6648161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 6656882SBrad.Beckmann@amd.com iter->start, iter->end); 6666882SBrad.Beckmann@amd.com return true; 6676882SBrad.Beckmann@amd.com } 6686882SBrad.Beckmann@amd.com } 6696882SBrad.Beckmann@amd.com return false; 6706882SBrad.Beckmann@amd.com} 6717909Shestness@cs.utexas.edu 6727909Shestness@cs.utexas.eduunsigned 6737909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 6747909Shestness@cs.utexas.edu{ 6757909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 6767909Shestness@cs.utexas.edu} 677