RubyPort.cc revision 8505
16876Ssteve.reinhardt@amd.com/* 26876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 36876Ssteve.reinhardt@amd.com * All rights reserved. 46876Ssteve.reinhardt@amd.com * 56876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 66876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 76876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 86876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 96876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 106876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 126876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 136876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 146876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 156876Ssteve.reinhardt@amd.com * 166876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276876Ssteve.reinhardt@amd.com */ 286876Ssteve.reinhardt@amd.com 297908Shestness@cs.utexas.edu#include "config/the_isa.hh" 307908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 317908Shestness@cs.utexas.edu#include "arch/x86/insts/microldstop.hh" 327908Shestness@cs.utexas.edu#endif // X86_ISA 337632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 348232Snate@binkert.org#include "debug/Ruby.hh" 358436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 367039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 376285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 388229Snate@binkert.org#include "mem/physical.hh" 396285Snate@binkert.org 406876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 416893SBrad.Beckmann@amd.com : MemObject(p) 426876Ssteve.reinhardt@amd.com{ 436876Ssteve.reinhardt@amd.com m_version = p->version; 446876Ssteve.reinhardt@amd.com assert(m_version != -1); 456876Ssteve.reinhardt@amd.com 466893SBrad.Beckmann@amd.com physmem = p->physmem; 477039Snate@binkert.org 486882SBrad.Beckmann@amd.com m_controller = NULL; 496882SBrad.Beckmann@amd.com m_mandatory_q_ptr = NULL; 506876Ssteve.reinhardt@amd.com 516876Ssteve.reinhardt@amd.com m_request_cnt = 0; 526882SBrad.Beckmann@amd.com pio_port = NULL; 536893SBrad.Beckmann@amd.com physMemPort = NULL; 547910SBrad.Beckmann@amd.com 557910SBrad.Beckmann@amd.com m_usingRubyTester = p->using_ruby_tester; 567915SBrad.Beckmann@amd.com access_phys_mem = p->access_phys_mem; 578436SBrad.Beckmann@amd.com 588436SBrad.Beckmann@amd.com ruby_system = p->ruby_system; 598505Snilay@cs.wisc.edu waitingOnSequencer = false; 606876Ssteve.reinhardt@amd.com} 616876Ssteve.reinhardt@amd.com 627039Snate@binkert.orgvoid 637039Snate@binkert.orgRubyPort::init() 646882SBrad.Beckmann@amd.com{ 656882SBrad.Beckmann@amd.com assert(m_controller != NULL); 666882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 676882SBrad.Beckmann@amd.com} 686882SBrad.Beckmann@amd.com 696876Ssteve.reinhardt@amd.comPort * 706876Ssteve.reinhardt@amd.comRubyPort::getPort(const std::string &if_name, int idx) 716876Ssteve.reinhardt@amd.com{ 726882SBrad.Beckmann@amd.com if (if_name == "port") { 737915SBrad.Beckmann@amd.com return new M5Port(csprintf("%s-port%d", name(), idx), this, 748436SBrad.Beckmann@amd.com ruby_system, access_phys_mem); 757039Snate@binkert.org } 767039Snate@binkert.org 777039Snate@binkert.org if (if_name == "pio_port") { 786882SBrad.Beckmann@amd.com // ensure there is only one pio port 796882SBrad.Beckmann@amd.com assert(pio_port == NULL); 806882SBrad.Beckmann@amd.com 817039Snate@binkert.org pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this); 826882SBrad.Beckmann@amd.com 836882SBrad.Beckmann@amd.com return pio_port; 847039Snate@binkert.org } 857039Snate@binkert.org 867039Snate@binkert.org if (if_name == "physMemPort") { 876893SBrad.Beckmann@amd.com // RubyPort should only have one port to physical memory 886893SBrad.Beckmann@amd.com assert (physMemPort == NULL); 896893SBrad.Beckmann@amd.com 907915SBrad.Beckmann@amd.com physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, 918436SBrad.Beckmann@amd.com ruby_system, access_phys_mem); 927039Snate@binkert.org 936893SBrad.Beckmann@amd.com return physMemPort; 947039Snate@binkert.org } 957039Snate@binkert.org 967039Snate@binkert.org if (if_name == "functional") { 977039Snate@binkert.org // Calls for the functional port only want to access 987039Snate@binkert.org // functional memory. Therefore, directly pass these calls 997039Snate@binkert.org // ports to physmem. 1006893SBrad.Beckmann@amd.com assert(physmem != NULL); 1016893SBrad.Beckmann@amd.com return physmem->getPort(if_name, idx); 1026882SBrad.Beckmann@amd.com } 1037039Snate@binkert.org 1046876Ssteve.reinhardt@amd.com return NULL; 1056876Ssteve.reinhardt@amd.com} 1066882SBrad.Beckmann@amd.com 1077039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1086882SBrad.Beckmann@amd.com RubyPort *_port) 1096882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1106882SBrad.Beckmann@amd.com{ 1118161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name); 1126882SBrad.Beckmann@amd.com ruby_port = _port; 1136882SBrad.Beckmann@amd.com} 1146882SBrad.Beckmann@amd.com 1158436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1168436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1176882SBrad.Beckmann@amd.com : SimpleTimingPort(_name, _port) 1186882SBrad.Beckmann@amd.com{ 1198161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name); 1206882SBrad.Beckmann@amd.com ruby_port = _port; 1218436SBrad.Beckmann@amd.com ruby_system = _system; 1227910SBrad.Beckmann@amd.com _onRetryList = false; 1237915SBrad.Beckmann@amd.com access_phys_mem = _access_phys_mem; 1246882SBrad.Beckmann@amd.com} 1256882SBrad.Beckmann@amd.com 1266882SBrad.Beckmann@amd.comTick 1276882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1286882SBrad.Beckmann@amd.com{ 1296882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1306882SBrad.Beckmann@amd.com return 0; 1316882SBrad.Beckmann@amd.com} 1326882SBrad.Beckmann@amd.com 1336882SBrad.Beckmann@amd.comTick 1346882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1356882SBrad.Beckmann@amd.com{ 1366882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1376882SBrad.Beckmann@amd.com return 0; 1386882SBrad.Beckmann@amd.com} 1396882SBrad.Beckmann@amd.com 1406882SBrad.Beckmann@amd.com 1416882SBrad.Beckmann@amd.combool 1426882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1436882SBrad.Beckmann@amd.com{ 1447039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1457039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1468161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1476882SBrad.Beckmann@amd.com 1486882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1496882SBrad.Beckmann@amd.com 1506882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1517039Snate@binkert.org RubyPort::SenderState *senderState = 1526882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1536882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1546882SBrad.Beckmann@amd.com assert(port != NULL); 1557039Snate@binkert.org 1566882SBrad.Beckmann@amd.com // pop the sender state from the packet 1576882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1586882SBrad.Beckmann@amd.com delete senderState; 1597039Snate@binkert.org 1606882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1617039Snate@binkert.org 1626882SBrad.Beckmann@amd.com return true; 1636882SBrad.Beckmann@amd.com} 1646882SBrad.Beckmann@amd.com 1656882SBrad.Beckmann@amd.combool 1666882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1676882SBrad.Beckmann@amd.com{ 1688161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1697039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1706882SBrad.Beckmann@amd.com 1716882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1726882SBrad.Beckmann@amd.com 1737039Snate@binkert.org // The received packets should only be M5 requests, which should never 1747039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1757039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1766882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1776882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1786882SBrad.Beckmann@amd.com 1796882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1806882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1816882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1826882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1836882SBrad.Beckmann@amd.com delete pkt; 1846882SBrad.Beckmann@amd.com return true; 1856882SBrad.Beckmann@amd.com } 1866882SBrad.Beckmann@amd.com 1876922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1886922SBrad.Beckmann@amd.com // route the response 1896922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1906922SBrad.Beckmann@amd.com 1916882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1926882SBrad.Beckmann@amd.com // pio port. 1936882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1946882SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 1958161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1966922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1976922SBrad.Beckmann@amd.com pkt->getAddr()); 1986882SBrad.Beckmann@amd.com 1996882SBrad.Beckmann@amd.com return ruby_port->pio_port->sendTiming(pkt); 2006882SBrad.Beckmann@amd.com } 2016882SBrad.Beckmann@amd.com 2026882SBrad.Beckmann@amd.com // For DMA and CPU requests, translate them to ruby requests before 2036882SBrad.Beckmann@amd.com // sending them to our assigned ruby port. 2046882SBrad.Beckmann@amd.com RubyRequestType type = RubyRequestType_NULL; 2056899SBrad.Beckmann@amd.com 2066899SBrad.Beckmann@amd.com // If valid, copy the pc to the ruby request 2076882SBrad.Beckmann@amd.com Addr pc = 0; 2086899SBrad.Beckmann@amd.com if (pkt->req->hasPC()) { 2096899SBrad.Beckmann@amd.com pc = pkt->req->getPC(); 2106899SBrad.Beckmann@amd.com } 2116899SBrad.Beckmann@amd.com 2127023SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 2137023SBrad.Beckmann@amd.com if (pkt->isWrite()) { 2148161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing SC\n"); 2157907Shestness@cs.utexas.edu type = RubyRequestType_Store_Conditional; 2166882SBrad.Beckmann@amd.com } else { 2178161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing LL\n"); 2187023SBrad.Beckmann@amd.com assert(pkt->isRead()); 2197907Shestness@cs.utexas.edu type = RubyRequestType_Load_Linked; 2206882SBrad.Beckmann@amd.com } 2217908Shestness@cs.utexas.edu } else if (pkt->req->isLocked()) { 2227908Shestness@cs.utexas.edu if (pkt->isWrite()) { 2238161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Write\n"); 2247908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Write; 2257908Shestness@cs.utexas.edu } else { 2268161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Issuing Locked RMW Read\n"); 2277908Shestness@cs.utexas.edu assert(pkt->isRead()); 2287908Shestness@cs.utexas.edu type = RubyRequestType_Locked_RMW_Read; 2297908Shestness@cs.utexas.edu } 2306922SBrad.Beckmann@amd.com } else { 2317023SBrad.Beckmann@amd.com if (pkt->isRead()) { 2327023SBrad.Beckmann@amd.com if (pkt->req->isInstFetch()) { 2337023SBrad.Beckmann@amd.com type = RubyRequestType_IFETCH; 2347023SBrad.Beckmann@amd.com } else { 2357908Shestness@cs.utexas.edu#if THE_ISA == X86_ISA 2367908Shestness@cs.utexas.edu uint32_t flags = pkt->req->getFlags(); 2377908Shestness@cs.utexas.edu bool storeCheck = flags & 2387908Shestness@cs.utexas.edu (TheISA::StoreCheck << TheISA::FlagShift); 2397908Shestness@cs.utexas.edu#else 2407908Shestness@cs.utexas.edu bool storeCheck = false; 2417908Shestness@cs.utexas.edu#endif // X86_ISA 2427908Shestness@cs.utexas.edu if (storeCheck) { 2437908Shestness@cs.utexas.edu type = RubyRequestType_RMW_Read; 2447908Shestness@cs.utexas.edu } else { 2457908Shestness@cs.utexas.edu type = RubyRequestType_LD; 2467908Shestness@cs.utexas.edu } 2477023SBrad.Beckmann@amd.com } 2487023SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2497908Shestness@cs.utexas.edu // 2507908Shestness@cs.utexas.edu // Note: M5 packets do not differentiate ST from RMW_Write 2517908Shestness@cs.utexas.edu // 2527023SBrad.Beckmann@amd.com type = RubyRequestType_ST; 2538184Ssomayeh@cs.wisc.edu } else if (pkt->isFlush()) { 2548184Ssomayeh@cs.wisc.edu type = RubyRequestType_FLUSH; 2557023SBrad.Beckmann@amd.com } else { 2567023SBrad.Beckmann@amd.com panic("Unsupported ruby packet type\n"); 2577023SBrad.Beckmann@amd.com } 2586882SBrad.Beckmann@amd.com } 2596882SBrad.Beckmann@amd.com 2607915SBrad.Beckmann@amd.com RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true), 2617039Snate@binkert.org pkt->getSize(), pc, type, 2627039Snate@binkert.org RubyAccessMode_Supervisor, pkt); 2636882SBrad.Beckmann@amd.com 2648174Snilay@cs.wisc.edu assert(ruby_request.m_PhysicalAddress.getOffset() + ruby_request.m_Size <= 2657906SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2667906SBrad.Beckmann@amd.com 2676882SBrad.Beckmann@amd.com // Submit the ruby request 2686922SBrad.Beckmann@amd.com RequestStatus requestStatus = ruby_port->makeRequest(ruby_request); 2697023SBrad.Beckmann@amd.com 2707550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2717023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2727023SBrad.Beckmann@amd.com // false. 2737550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2748161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2756922SBrad.Beckmann@amd.com return true; 2766882SBrad.Beckmann@amd.com } 2777023SBrad.Beckmann@amd.com 2787910SBrad.Beckmann@amd.com // 2797910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2807910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2817910SBrad.Beckmann@amd.com // 2827910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2837910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2847910SBrad.Beckmann@amd.com } 2857910SBrad.Beckmann@amd.com 2868161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2877906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2887039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2897039Snate@binkert.org 2906922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2916922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2926922SBrad.Beckmann@amd.com delete senderState; 2936922SBrad.Beckmann@amd.com return false; 2946882SBrad.Beckmann@amd.com} 2956882SBrad.Beckmann@amd.com 2968436SBrad.Beckmann@amd.combool 2978436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 2988436SBrad.Beckmann@amd.com{ 2998436SBrad.Beckmann@amd.com Address address(pkt->getAddr()); 3008436SBrad.Beckmann@amd.com Address line_address(address); 3018436SBrad.Beckmann@amd.com line_address.makeLineAddress(); 3028436SBrad.Beckmann@amd.com 3038436SBrad.Beckmann@amd.com AccessPermission accessPerm = AccessPermission_NotPresent; 3048436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3058436SBrad.Beckmann@amd.com 3068436SBrad.Beckmann@amd.com // In this loop, we try to figure which controller has a read only or 3078436SBrad.Beckmann@amd.com // a read write copy of the given address. Any valid copy would suffice 3088436SBrad.Beckmann@amd.com // for a functional read. 3098436SBrad.Beckmann@amd.com 3108436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Read request for %s\n",address); 3118436SBrad.Beckmann@amd.com for(int i = 0;i < num_controllers;++i) 3128436SBrad.Beckmann@amd.com { 3138436SBrad.Beckmann@amd.com accessPerm = ruby_system->m_abs_cntrl_vec[i] 3148436SBrad.Beckmann@amd.com ->getAccessPermission(line_address); 3158436SBrad.Beckmann@amd.com if(accessPerm == AccessPermission_Read_Only || 3168436SBrad.Beckmann@amd.com accessPerm == AccessPermission_Read_Write) 3178436SBrad.Beckmann@amd.com { 3188436SBrad.Beckmann@amd.com unsigned startByte = address.getAddress() - line_address.getAddress(); 3198436SBrad.Beckmann@amd.com 3208436SBrad.Beckmann@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3218436SBrad.Beckmann@amd.com unsigned int size_in_bytes = pkt->getSize(); 3228436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3238436SBrad.Beckmann@amd.com ->getDataBlock(line_address); 3248436SBrad.Beckmann@amd.com 3258436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3268436SBrad.Beckmann@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3278436SBrad.Beckmann@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) 3288436SBrad.Beckmann@amd.com { 3298436SBrad.Beckmann@amd.com data[i] = block.getByte(i + startByte); 3308436SBrad.Beckmann@amd.com } 3318436SBrad.Beckmann@amd.com return true; 3328436SBrad.Beckmann@amd.com } 3338436SBrad.Beckmann@amd.com } 3348436SBrad.Beckmann@amd.com return false; 3358436SBrad.Beckmann@amd.com} 3368436SBrad.Beckmann@amd.com 3378436SBrad.Beckmann@amd.combool 3388436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 3398436SBrad.Beckmann@amd.com{ 3408436SBrad.Beckmann@amd.com Address addr(pkt->getAddr()); 3418436SBrad.Beckmann@amd.com Address line_addr = line_address(addr); 3428436SBrad.Beckmann@amd.com AccessPermission accessPerm = AccessPermission_NotPresent; 3438436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3448436SBrad.Beckmann@amd.com 3458436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 3468436SBrad.Beckmann@amd.com 3478436SBrad.Beckmann@amd.com unsigned int num_ro = 0; 3488436SBrad.Beckmann@amd.com unsigned int num_rw = 0; 3498436SBrad.Beckmann@amd.com unsigned int num_busy = 0; 3508436SBrad.Beckmann@amd.com 3518436SBrad.Beckmann@amd.com // In this loop we count the number of controllers that have the given 3528436SBrad.Beckmann@amd.com // address in read only, read write and busy states. 3538436SBrad.Beckmann@amd.com for(int i = 0;i < num_controllers;++i) 3548436SBrad.Beckmann@amd.com { 3558436SBrad.Beckmann@amd.com accessPerm = ruby_system->m_abs_cntrl_vec[i]-> 3568436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3578436SBrad.Beckmann@amd.com if(accessPerm == AccessPermission_Read_Only) num_ro++; 3588436SBrad.Beckmann@amd.com else if(accessPerm == AccessPermission_Read_Write) num_rw++; 3598436SBrad.Beckmann@amd.com else if(accessPerm == AccessPermission_Busy) num_busy++; 3608436SBrad.Beckmann@amd.com } 3618436SBrad.Beckmann@amd.com 3628436SBrad.Beckmann@amd.com // If the number of read write copies is more than 1, then there is bug in 3638436SBrad.Beckmann@amd.com // coherence protocol. Otherwise, if all copies are in stable states, i.e. 3648436SBrad.Beckmann@amd.com // num_busy == 0, we update all the copies. If there is at least one copy 3658436SBrad.Beckmann@amd.com // in busy state, then we check if there is read write copy. If yes, then 3668436SBrad.Beckmann@amd.com // also we let the access go through. 3678436SBrad.Beckmann@amd.com 3688436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3698436SBrad.Beckmann@amd.com num_busy, num_ro, num_rw); 3708436SBrad.Beckmann@amd.com assert(num_rw <= 1); 3718436SBrad.Beckmann@amd.com if((num_busy == 0 && num_ro > 0) || num_rw == 1) 3728436SBrad.Beckmann@amd.com { 3738436SBrad.Beckmann@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3748436SBrad.Beckmann@amd.com unsigned int size_in_bytes = pkt->getSize(); 3758436SBrad.Beckmann@amd.com unsigned startByte = addr.getAddress() - line_addr.getAddress(); 3768436SBrad.Beckmann@amd.com 3778436SBrad.Beckmann@amd.com for(int i = 0; i < num_controllers;++i) 3788436SBrad.Beckmann@amd.com { 3798436SBrad.Beckmann@amd.com accessPerm = ruby_system->m_abs_cntrl_vec[i]-> 3808436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3818436SBrad.Beckmann@amd.com if(accessPerm == AccessPermission_Read_Only || 3828436SBrad.Beckmann@amd.com accessPerm == AccessPermission_Read_Write|| 3838436SBrad.Beckmann@amd.com accessPerm == AccessPermission_Maybe_Stale) 3848436SBrad.Beckmann@amd.com { 3858436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3868436SBrad.Beckmann@amd.com ->getDataBlock(line_addr); 3878436SBrad.Beckmann@amd.com 3888436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 3898436SBrad.Beckmann@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) 3908436SBrad.Beckmann@amd.com { 3918436SBrad.Beckmann@amd.com block.setByte(i + startByte, data[i]); 3928436SBrad.Beckmann@amd.com } 3938436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 3948436SBrad.Beckmann@amd.com } 3958436SBrad.Beckmann@amd.com } 3968436SBrad.Beckmann@amd.com return true; 3978436SBrad.Beckmann@amd.com } 3988436SBrad.Beckmann@amd.com return false; 3998436SBrad.Beckmann@amd.com} 4008436SBrad.Beckmann@amd.com 4018436SBrad.Beckmann@amd.comvoid 4028436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 4038436SBrad.Beckmann@amd.com{ 4048436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 4058436SBrad.Beckmann@amd.com pkt->getAddr()); 4068436SBrad.Beckmann@amd.com 4078436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 4088436SBrad.Beckmann@amd.com // pio port. 4098436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 4108436SBrad.Beckmann@amd.com assert(ruby_port->pio_port != NULL); 4118436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 4128436SBrad.Beckmann@amd.com pkt->getAddr()); 4138436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 4148436SBrad.Beckmann@amd.com } 4158436SBrad.Beckmann@amd.com 4168436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 4178436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 4188436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 4198436SBrad.Beckmann@amd.com 4208436SBrad.Beckmann@amd.com bool accessSucceeded = false; 4218436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4228436SBrad.Beckmann@amd.com 4238436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 4248436SBrad.Beckmann@amd.com if (pkt->isRead()) { 4258436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalRead(pkt); 4268436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 4278436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalWrite(pkt); 4288436SBrad.Beckmann@amd.com } else { 4298436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 4308436SBrad.Beckmann@amd.com pkt->cmdString()); 4318436SBrad.Beckmann@amd.com } 4328436SBrad.Beckmann@amd.com 4338436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 4348436SBrad.Beckmann@amd.com // the functional request failed 4358436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 4368436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 4378436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 4388436SBrad.Beckmann@amd.com } 4398436SBrad.Beckmann@amd.com 4408436SBrad.Beckmann@amd.com if (access_phys_mem) { 4418436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 4428436SBrad.Beckmann@amd.com // The following command performs the real functional access. 4438436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 4448436SBrad.Beckmann@amd.com // of data. 4458436SBrad.Beckmann@amd.com ruby_port->physMemPort->sendFunctional(pkt); 4468436SBrad.Beckmann@amd.com } 4478436SBrad.Beckmann@amd.com 4488436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4498436SBrad.Beckmann@amd.com if (needsResponse) { 4508436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 4518436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4528436SBrad.Beckmann@amd.com sendFunctional(pkt); 4538436SBrad.Beckmann@amd.com } 4548436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 4558436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 4568436SBrad.Beckmann@amd.com} 4578436SBrad.Beckmann@amd.com 4586882SBrad.Beckmann@amd.comvoid 4596922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 4606882SBrad.Beckmann@amd.com{ 4616922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 4627039Snate@binkert.org RubyPort::SenderState *senderState = 4636922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 4646922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 4656922SBrad.Beckmann@amd.com assert(port != NULL); 4667039Snate@binkert.org 4676922SBrad.Beckmann@amd.com // pop the sender state from the packet 4686922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 4696922SBrad.Beckmann@amd.com delete senderState; 4706882SBrad.Beckmann@amd.com 4716882SBrad.Beckmann@amd.com port->hitCallback(pkt); 4727910SBrad.Beckmann@amd.com 4737910SBrad.Beckmann@amd.com // 4747910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 4757910SBrad.Beckmann@amd.com // likely has free resources now. 4767910SBrad.Beckmann@amd.com // 4777910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 4788162SBrad.Beckmann@amd.com // 4798162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 4808162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 4818162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 4828162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 4838162SBrad.Beckmann@amd.com // sendRetry. 4848162SBrad.Beckmann@amd.com // 4858162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 4868162SBrad.Beckmann@amd.com 4878162SBrad.Beckmann@amd.com retryList.clear(); 4888162SBrad.Beckmann@amd.com waitingOnSequencer = false; 4898162SBrad.Beckmann@amd.com 4908162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 4918162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 4928162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 4937910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 4947910SBrad.Beckmann@amd.com (*i)->name()); 4958162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 4968162SBrad.Beckmann@amd.com (*i)->sendRetry(); 4977910SBrad.Beckmann@amd.com } 4987910SBrad.Beckmann@amd.com } 4996882SBrad.Beckmann@amd.com} 5006882SBrad.Beckmann@amd.com 5016882SBrad.Beckmann@amd.comvoid 5026882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 5036882SBrad.Beckmann@amd.com{ 5046882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 5056882SBrad.Beckmann@amd.com 5067550SBrad.Beckmann@amd.com // 5077915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 5088184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 5097550SBrad.Beckmann@amd.com // 5107915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 5117550SBrad.Beckmann@amd.com 5127550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 5137550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 5147550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 5157550SBrad.Beckmann@amd.com // 5167550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 5177550SBrad.Beckmann@amd.com // 5187550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 5197550SBrad.Beckmann@amd.com } else { 5207550SBrad.Beckmann@amd.com // 5217550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 5227550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 5237550SBrad.Beckmann@amd.com // 5247550SBrad.Beckmann@amd.com accessPhysMem = false; 5257550SBrad.Beckmann@amd.com } 5267550SBrad.Beckmann@amd.com } else { 5277550SBrad.Beckmann@amd.com // 5287550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 5297550SBrad.Beckmann@amd.com // not lock the blocks. 5307550SBrad.Beckmann@amd.com // 5317550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 5327550SBrad.Beckmann@amd.com } 5337550SBrad.Beckmann@amd.com } 5348184Ssomayeh@cs.wisc.edu 5358184Ssomayeh@cs.wisc.edu // 5368184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 5378184Ssomayeh@cs.wisc.edu // 5388184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 5398184Ssomayeh@cs.wisc.edu accessPhysMem = false; 5408184Ssomayeh@cs.wisc.edu } 5418184Ssomayeh@cs.wisc.edu 5428161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 5436882SBrad.Beckmann@amd.com 5447550SBrad.Beckmann@amd.com if (accessPhysMem) { 5457550SBrad.Beckmann@amd.com ruby_port->physMemPort->sendAtomic(pkt); 5468184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 5477915SBrad.Beckmann@amd.com pkt->makeResponse(); 5487550SBrad.Beckmann@amd.com } 5496882SBrad.Beckmann@amd.com 5506882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 5516882SBrad.Beckmann@amd.com if (needsResponse) { 5528161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 5536882SBrad.Beckmann@amd.com sendTiming(pkt); 5546882SBrad.Beckmann@amd.com } else { 5556882SBrad.Beckmann@amd.com delete pkt; 5566882SBrad.Beckmann@amd.com } 5578161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 5586882SBrad.Beckmann@amd.com} 5596882SBrad.Beckmann@amd.com 5606882SBrad.Beckmann@amd.combool 5616882SBrad.Beckmann@amd.comRubyPort::M5Port::sendTiming(PacketPtr pkt) 5626882SBrad.Beckmann@amd.com{ 5637558SBrad.Beckmann@amd.com //minimum latency, must be > 0 5647823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 5656882SBrad.Beckmann@amd.com return true; 5666882SBrad.Beckmann@amd.com} 5676882SBrad.Beckmann@amd.com 5686882SBrad.Beckmann@amd.combool 5696882SBrad.Beckmann@amd.comRubyPort::PioPort::sendTiming(PacketPtr pkt) 5706882SBrad.Beckmann@amd.com{ 5717558SBrad.Beckmann@amd.com //minimum latency, must be > 0 5727823Ssteve.reinhardt@amd.com schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 5736882SBrad.Beckmann@amd.com return true; 5746882SBrad.Beckmann@amd.com} 5756882SBrad.Beckmann@amd.com 5766882SBrad.Beckmann@amd.combool 5776882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 5786882SBrad.Beckmann@amd.com{ 5796882SBrad.Beckmann@amd.com AddrRangeList physMemAddrList; 5806882SBrad.Beckmann@amd.com bool snoop = false; 5816893SBrad.Beckmann@amd.com ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop); 5827039Snate@binkert.org for (AddrRangeIter iter = physMemAddrList.begin(); 5837039Snate@binkert.org iter != physMemAddrList.end(); 5847039Snate@binkert.org iter++) { 5856882SBrad.Beckmann@amd.com if (addr >= iter->start && addr <= iter->end) { 5868161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 5876882SBrad.Beckmann@amd.com iter->start, iter->end); 5886882SBrad.Beckmann@amd.com return true; 5896882SBrad.Beckmann@amd.com } 5906882SBrad.Beckmann@amd.com } 5916882SBrad.Beckmann@amd.com return false; 5926882SBrad.Beckmann@amd.com} 5937909Shestness@cs.utexas.edu 5947909Shestness@cs.utexas.eduunsigned 5957909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 5967909Shestness@cs.utexas.edu{ 5977909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 5987909Shestness@cs.utexas.edu} 599