RubyPort.cc revision 10525
16876Ssteve.reinhardt@amd.com/* 210089Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 4910525Snilay@cs.wisc.edu#include "mem/simple_mem.hh" 5010117Snilay@cs.wisc.edu#include "sim/full_system.hh" 518923Sandreas.hansson@arm.com#include "sim/system.hh" 526285Snate@binkert.org 536876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 548922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 5510090Snilay@cs.wisc.edu m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 5610467Sandreas.hansson@arm.com system(p->system), 5710090Snilay@cs.wisc.edu pioMasterPort(csprintf("%s.pio-master-port", name()), this), 5810090Snilay@cs.wisc.edu pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 5910090Snilay@cs.wisc.edu memMasterPort(csprintf("%s.mem-master-port", name()), this), 6010090Snilay@cs.wisc.edu memSlavePort(csprintf("%s-mem-slave-port", name()), this, 6110525Snilay@cs.wisc.edu p->ruby_system, p->access_backing_store, -1), 6210525Snilay@cs.wisc.edu gotAddrRanges(p->port_master_connection_count), drainManager(NULL) 636876Ssteve.reinhardt@amd.com{ 646876Ssteve.reinhardt@amd.com assert(m_version != -1); 656876Ssteve.reinhardt@amd.com 668922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 678922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 6810090Snilay@cs.wisc.edu slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 6910525Snilay@cs.wisc.edu i), this, p->ruby_system, p->access_backing_store, i)); 708922Swilliam.wang@arm.com } 717039Snate@binkert.org 728922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 738922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 7410090Snilay@cs.wisc.edu master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 7510090Snilay@cs.wisc.edu name(), i), this)); 768922Swilliam.wang@arm.com } 776876Ssteve.reinhardt@amd.com} 786876Ssteve.reinhardt@amd.com 797039Snate@binkert.orgvoid 807039Snate@binkert.orgRubyPort::init() 816882SBrad.Beckmann@amd.com{ 826882SBrad.Beckmann@amd.com assert(m_controller != NULL); 836882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 849508Snilay@cs.wisc.edu m_mandatory_q_ptr->setSender(this); 856882SBrad.Beckmann@amd.com} 866882SBrad.Beckmann@amd.com 879294Sandreas.hansson@arm.comBaseMasterPort & 889294Sandreas.hansson@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 896876Ssteve.reinhardt@amd.com{ 9010090Snilay@cs.wisc.edu if (if_name == "mem_master_port") { 9110090Snilay@cs.wisc.edu return memMasterPort; 9210090Snilay@cs.wisc.edu } 9310090Snilay@cs.wisc.edu 9410090Snilay@cs.wisc.edu if (if_name == "pio_master_port") { 9510090Snilay@cs.wisc.edu return pioMasterPort; 968922Swilliam.wang@arm.com } 978922Swilliam.wang@arm.com 988839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 998839Sandreas.hansson@arm.com // port 1008922Swilliam.wang@arm.com if (if_name != "master") { 1018922Swilliam.wang@arm.com // pass it along to our super class 1028922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1038922Swilliam.wang@arm.com } else { 1049294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 1058922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 1068922Swilliam.wang@arm.com } 1078839Sandreas.hansson@arm.com 1088922Swilliam.wang@arm.com return *master_ports[idx]; 1098839Sandreas.hansson@arm.com } 1108922Swilliam.wang@arm.com} 1118839Sandreas.hansson@arm.com 1129294Sandreas.hansson@arm.comBaseSlavePort & 1139294Sandreas.hansson@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 1148922Swilliam.wang@arm.com{ 11510090Snilay@cs.wisc.edu if (if_name == "mem_slave_port") { 11610090Snilay@cs.wisc.edu return memSlavePort; 11710090Snilay@cs.wisc.edu } 11810090Snilay@cs.wisc.edu 11910090Snilay@cs.wisc.edu if (if_name == "pio_slave_port") 12010090Snilay@cs.wisc.edu return pioSlavePort; 12110090Snilay@cs.wisc.edu 1228922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1238922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1248922Swilliam.wang@arm.com if (if_name != "slave") { 1258922Swilliam.wang@arm.com // pass it along to our super class 1268922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1278922Swilliam.wang@arm.com } else { 1289294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 1298922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1308922Swilliam.wang@arm.com } 1318922Swilliam.wang@arm.com 1328922Swilliam.wang@arm.com return *slave_ports[idx]; 1337039Snate@binkert.org } 1346876Ssteve.reinhardt@amd.com} 1356882SBrad.Beckmann@amd.com 13610090Snilay@cs.wisc.eduRubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 1376882SBrad.Beckmann@amd.com RubyPort *_port) 13810090Snilay@cs.wisc.edu : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 1396882SBrad.Beckmann@amd.com{ 14010090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 1416882SBrad.Beckmann@amd.com} 1426882SBrad.Beckmann@amd.com 14310090Snilay@cs.wisc.eduRubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 14410090Snilay@cs.wisc.edu RubyPort *_port) 14510090Snilay@cs.wisc.edu : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 14610090Snilay@cs.wisc.edu{ 14710090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 14810090Snilay@cs.wisc.edu} 14910090Snilay@cs.wisc.edu 15010090Snilay@cs.wisc.eduRubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 15110090Snilay@cs.wisc.edu RubyPort *_port) 15210090Snilay@cs.wisc.edu : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 15310090Snilay@cs.wisc.edu{ 15410090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 15510090Snilay@cs.wisc.edu} 15610090Snilay@cs.wisc.edu 15710090Snilay@cs.wisc.eduRubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 15810525Snilay@cs.wisc.edu RubySystem *_system, 15910525Snilay@cs.wisc.edu bool _access_backing_store, PortID id) 16010089Sandreas.hansson@arm.com : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 16110525Snilay@cs.wisc.edu ruby_system(_system), access_backing_store(_access_backing_store) 1626882SBrad.Beckmann@amd.com{ 16310090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 1646882SBrad.Beckmann@amd.com} 1656882SBrad.Beckmann@amd.com 16610089Sandreas.hansson@arm.combool 16710090Snilay@cs.wisc.eduRubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 16810090Snilay@cs.wisc.edu{ 16910090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 17010090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 17110090Snilay@cs.wisc.edu 17210090Snilay@cs.wisc.edu // send next cycle 17310090Snilay@cs.wisc.edu ruby_port->pioSlavePort.schedTimingResp( 17410090Snilay@cs.wisc.edu pkt, curTick() + g_system_ptr->clockPeriod()); 17510090Snilay@cs.wisc.edu return true; 17610090Snilay@cs.wisc.edu} 17710090Snilay@cs.wisc.edu 17810090Snilay@cs.wisc.edubool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 17910089Sandreas.hansson@arm.com{ 18010089Sandreas.hansson@arm.com // got a response from a device 18110089Sandreas.hansson@arm.com assert(pkt->isResponse()); 1826882SBrad.Beckmann@amd.com 1837039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1847039Snate@binkert.org // and it must forward these responses back to the particular CPU. 18510089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Pio response for address %#x, going to %d\n", 18610089Sandreas.hansson@arm.com pkt->getAddr(), pkt->getDest()); 1876882SBrad.Beckmann@amd.com 18810090Snilay@cs.wisc.edu // First we must retrieve the request port from the sender State 18910090Snilay@cs.wisc.edu RubyPort::SenderState *senderState = 19010090Snilay@cs.wisc.edu safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 19110090Snilay@cs.wisc.edu MemSlavePort *port = senderState->port; 19210090Snilay@cs.wisc.edu assert(port != NULL); 19310090Snilay@cs.wisc.edu delete senderState; 1947039Snate@binkert.org 19510089Sandreas.hansson@arm.com // attempt to send the response in the next cycle 19610090Snilay@cs.wisc.edu port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 1977039Snate@binkert.org 1986882SBrad.Beckmann@amd.com return true; 1996882SBrad.Beckmann@amd.com} 2006882SBrad.Beckmann@amd.com 2016882SBrad.Beckmann@amd.combool 20210090Snilay@cs.wisc.eduRubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 2036882SBrad.Beckmann@amd.com{ 20410090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 20510090Snilay@cs.wisc.edu 20610090Snilay@cs.wisc.edu for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 20710090Snilay@cs.wisc.edu AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 20810090Snilay@cs.wisc.edu for (auto it = l.begin(); it != l.end(); ++it) { 20910090Snilay@cs.wisc.edu if (it->contains(pkt->getAddr())) { 21010412Sandreas.hansson@arm.com // generally it is not safe to assume success here as 21110412Sandreas.hansson@arm.com // the port could be blocked 21210412Sandreas.hansson@arm.com bool M5_VAR_USED success = 21310412Sandreas.hansson@arm.com ruby_port->master_ports[i]->sendTimingReq(pkt); 21410412Sandreas.hansson@arm.com assert(success); 21510090Snilay@cs.wisc.edu return true; 21610090Snilay@cs.wisc.edu } 21710090Snilay@cs.wisc.edu } 21810090Snilay@cs.wisc.edu } 21910090Snilay@cs.wisc.edu panic("Should never reach here!\n"); 22010090Snilay@cs.wisc.edu} 22110090Snilay@cs.wisc.edu 22210090Snilay@cs.wisc.edubool 22310090Snilay@cs.wisc.eduRubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 22410090Snilay@cs.wisc.edu{ 22510090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 22610090Snilay@cs.wisc.edu pkt->getAddr(), id); 22710090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 2286882SBrad.Beckmann@amd.com 2299662Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) 2309662Sandreas.hansson@arm.com panic("RubyPort should never see an inhibited request\n"); 2316882SBrad.Beckmann@amd.com 2326882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2336882SBrad.Beckmann@amd.com // pio port. 2346882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 23510090Snilay@cs.wisc.edu assert(ruby_port->memMasterPort.isConnected()); 23610090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 2376922SBrad.Beckmann@amd.com pkt->getAddr()); 2386882SBrad.Beckmann@amd.com 23910090Snilay@cs.wisc.edu // Save the port in the sender state object to be used later to 24010090Snilay@cs.wisc.edu // route the response 24110090Snilay@cs.wisc.edu pkt->pushSenderState(new SenderState(this)); 24210090Snilay@cs.wisc.edu 2439163Sandreas.hansson@arm.com // send next cycle 24410090Snilay@cs.wisc.edu ruby_port->memMasterPort.schedTimingReq(pkt, 2459206Snilay@cs.wisc.edu curTick() + g_system_ptr->clockPeriod()); 2469163Sandreas.hansson@arm.com return true; 2476882SBrad.Beckmann@amd.com } 2486882SBrad.Beckmann@amd.com 24910090Snilay@cs.wisc.edu // Save the port id to be used later to route the response 25010090Snilay@cs.wisc.edu pkt->setSrc(id); 25110090Snilay@cs.wisc.edu 2528615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 2538615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2547906SBrad.Beckmann@amd.com 2556882SBrad.Beckmann@amd.com // Submit the ruby request 2568615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2577023SBrad.Beckmann@amd.com 2587550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 25910089Sandreas.hansson@arm.com // Otherwise, we need to tell the port to retry at a later point 26010089Sandreas.hansson@arm.com // and return false. 2617550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 26210089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 26310089Sandreas.hansson@arm.com pkt->getAddr()); 2646922SBrad.Beckmann@amd.com return true; 2656882SBrad.Beckmann@amd.com } 2667023SBrad.Beckmann@amd.com 2677910SBrad.Beckmann@amd.com // 2687910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2697910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2707910SBrad.Beckmann@amd.com // 2717910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2727910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2737910SBrad.Beckmann@amd.com } 2747910SBrad.Beckmann@amd.com 27510090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 2767039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2777039Snate@binkert.org 2786922SBrad.Beckmann@amd.com return false; 2796882SBrad.Beckmann@amd.com} 2806882SBrad.Beckmann@amd.com 2818436SBrad.Beckmann@amd.comvoid 28210090Snilay@cs.wisc.eduRubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 2838436SBrad.Beckmann@amd.com{ 28410090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 2858436SBrad.Beckmann@amd.com 2868436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2878436SBrad.Beckmann@amd.com // pio port. 2888436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 28910525Snilay@cs.wisc.edu RubyPort *ruby_port M5_VAR_USED = static_cast<RubyPort *>(&owner); 29010090Snilay@cs.wisc.edu assert(ruby_port->memMasterPort.isConnected()); 29110090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 29210090Snilay@cs.wisc.edu panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 2938436SBrad.Beckmann@amd.com } 2948436SBrad.Beckmann@amd.com 2958436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 2968436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 2978436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2988436SBrad.Beckmann@amd.com 2998436SBrad.Beckmann@amd.com bool accessSucceeded = false; 3008436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 3018436SBrad.Beckmann@amd.com 3028436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 3038436SBrad.Beckmann@amd.com if (pkt->isRead()) { 3049270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalRead(pkt); 3058436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 3069270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalWrite(pkt); 3078436SBrad.Beckmann@amd.com } else { 30810090Snilay@cs.wisc.edu panic("Unsupported functional command %s\n", pkt->cmdString()); 3098436SBrad.Beckmann@amd.com } 3108436SBrad.Beckmann@amd.com 3118436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 3128436SBrad.Beckmann@amd.com // the functional request failed 3138436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 3148436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 3158436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 3168436SBrad.Beckmann@amd.com } 3178436SBrad.Beckmann@amd.com 31810525Snilay@cs.wisc.edu if (access_backing_store) { 3198436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 3208436SBrad.Beckmann@amd.com // The following command performs the real functional access. 3218436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 3228436SBrad.Beckmann@amd.com // of data. 32310525Snilay@cs.wisc.edu ruby_system->getPhysMem()->functionalAccess(pkt); 3248436SBrad.Beckmann@amd.com } 3258436SBrad.Beckmann@amd.com 3268436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 3278436SBrad.Beckmann@amd.com if (needsResponse) { 3288436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 32910525Snilay@cs.wisc.edu } 3308706Sandreas.hansson@arm.com 3318436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 3328436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 3338436SBrad.Beckmann@amd.com} 3348436SBrad.Beckmann@amd.com 3356882SBrad.Beckmann@amd.comvoid 3366922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 3376882SBrad.Beckmann@amd.com{ 33810089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 33910089Sandreas.hansson@arm.com pkt->getAddr()); 3407039Snate@binkert.org 34110089Sandreas.hansson@arm.com // The packet was destined for memory and has not yet been turned 34210089Sandreas.hansson@arm.com // into a response 34310089Sandreas.hansson@arm.com assert(system->isMemAddr(pkt->getAddr())); 34410089Sandreas.hansson@arm.com assert(pkt->isRequest()); 3456882SBrad.Beckmann@amd.com 34610089Sandreas.hansson@arm.com // As it has not yet been turned around, the source field tells us 34710089Sandreas.hansson@arm.com // which port it came from. 34810089Sandreas.hansson@arm.com assert(pkt->getSrc() < slave_ports.size()); 34910089Sandreas.hansson@arm.com 35010089Sandreas.hansson@arm.com slave_ports[pkt->getSrc()]->hitCallback(pkt); 3517910SBrad.Beckmann@amd.com 3527910SBrad.Beckmann@amd.com // 35310090Snilay@cs.wisc.edu // If we had to stall the MemSlavePorts, wake them up because the sequencer 3547910SBrad.Beckmann@amd.com // likely has free resources now. 3557910SBrad.Beckmann@amd.com // 35610089Sandreas.hansson@arm.com if (!retryList.empty()) { 3578162SBrad.Beckmann@amd.com // 3588162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3598162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3608162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3618162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3628162SBrad.Beckmann@amd.com // sendRetry. 3638162SBrad.Beckmann@amd.com // 36410090Snilay@cs.wisc.edu std::vector<MemSlavePort *> curRetryList(retryList); 3658162SBrad.Beckmann@amd.com 3668162SBrad.Beckmann@amd.com retryList.clear(); 36710089Sandreas.hansson@arm.com 36810089Sandreas.hansson@arm.com for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 3698162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3707910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3717910SBrad.Beckmann@amd.com (*i)->name()); 3728162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3737910SBrad.Beckmann@amd.com } 3747910SBrad.Beckmann@amd.com } 3758688Snilay@cs.wisc.edu 3768688Snilay@cs.wisc.edu testDrainComplete(); 3778688Snilay@cs.wisc.edu} 3788688Snilay@cs.wisc.edu 3798688Snilay@cs.wisc.eduvoid 3808688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 3818688Snilay@cs.wisc.edu{ 3828688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 3839342SAndreas.Sandberg@arm.com if (drainManager != NULL) { 3849245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 3859152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 3868688Snilay@cs.wisc.edu if (drainCount == 0) { 3879342SAndreas.Sandberg@arm.com DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 3889342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 3899342SAndreas.Sandberg@arm.com // Clear the drain manager once we're done with it. 3909342SAndreas.Sandberg@arm.com drainManager = NULL; 3918688Snilay@cs.wisc.edu } 3928688Snilay@cs.wisc.edu } 3938688Snilay@cs.wisc.edu} 3948688Snilay@cs.wisc.edu 3958688Snilay@cs.wisc.eduunsigned int 3969342SAndreas.Sandberg@arm.comRubyPort::getChildDrainCount(DrainManager *dm) 3978688Snilay@cs.wisc.edu{ 3988688Snilay@cs.wisc.edu int count = 0; 3998688Snilay@cs.wisc.edu 40010090Snilay@cs.wisc.edu if (memMasterPort.isConnected()) { 40110090Snilay@cs.wisc.edu count += memMasterPort.drain(dm); 4028688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 4038688Snilay@cs.wisc.edu } 4048688Snilay@cs.wisc.edu 4058922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 4069342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 4078922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 4088922Swilliam.wang@arm.com } 4098922Swilliam.wang@arm.com 41010090Snilay@cs.wisc.edu for (std::vector<PioMasterPort *>::iterator p = master_ports.begin(); 4118922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 4129342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 4138922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 4148688Snilay@cs.wisc.edu } 4158688Snilay@cs.wisc.edu 4168688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 4178688Snilay@cs.wisc.edu return count; 4188688Snilay@cs.wisc.edu} 4198688Snilay@cs.wisc.edu 4208688Snilay@cs.wisc.eduunsigned int 4219342SAndreas.Sandberg@arm.comRubyPort::drain(DrainManager *dm) 4228688Snilay@cs.wisc.edu{ 4238688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 4248688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 4258688Snilay@cs.wisc.edu } 4268688Snilay@cs.wisc.edu 4279245Shestness@cs.wisc.edu // 4289245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 4299342SAndreas.Sandberg@arm.com // requests before it should call drainManager->signalDrainDone() 4309245Shestness@cs.wisc.edu // 4319245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 4329245Shestness@cs.wisc.edu bool need_drain = outstandingCount() > 0; 4339245Shestness@cs.wisc.edu 4349245Shestness@cs.wisc.edu // 4359245Shestness@cs.wisc.edu // Also, get the number of child ports that will also need to clear 4369342SAndreas.Sandberg@arm.com // their buffered requests before they call drainManager->signalDrainDone() 4379245Shestness@cs.wisc.edu // 4389342SAndreas.Sandberg@arm.com unsigned int child_drain_count = getChildDrainCount(dm); 4398688Snilay@cs.wisc.edu 4408688Snilay@cs.wisc.edu // Set status 4419245Shestness@cs.wisc.edu if (need_drain) { 4429342SAndreas.Sandberg@arm.com drainManager = dm; 4438688Snilay@cs.wisc.edu 4449152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 4459342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 4469245Shestness@cs.wisc.edu return child_drain_count + 1; 4478688Snilay@cs.wisc.edu } 4488688Snilay@cs.wisc.edu 4499342SAndreas.Sandberg@arm.com drainManager = NULL; 4509342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 4519245Shestness@cs.wisc.edu return child_drain_count; 4526882SBrad.Beckmann@amd.com} 4536882SBrad.Beckmann@amd.com 4546882SBrad.Beckmann@amd.comvoid 45510090Snilay@cs.wisc.eduRubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 4566882SBrad.Beckmann@amd.com{ 4576882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4586882SBrad.Beckmann@amd.com 4597915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 4608184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 46110525Snilay@cs.wisc.edu bool accessPhysMem = access_backing_store; 4627550SBrad.Beckmann@amd.com 4637550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4647550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4657550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4667550SBrad.Beckmann@amd.com // 4677550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4687550SBrad.Beckmann@amd.com // 4697550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4707550SBrad.Beckmann@amd.com } else { 4717550SBrad.Beckmann@amd.com // 4727550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4737550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4747550SBrad.Beckmann@amd.com // 4757550SBrad.Beckmann@amd.com accessPhysMem = false; 4767550SBrad.Beckmann@amd.com } 4777550SBrad.Beckmann@amd.com } else { 4787550SBrad.Beckmann@amd.com // 4797550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4807550SBrad.Beckmann@amd.com // not lock the blocks. 4817550SBrad.Beckmann@amd.com // 4827550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4837550SBrad.Beckmann@amd.com } 4847550SBrad.Beckmann@amd.com } 4858184Ssomayeh@cs.wisc.edu 4868184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4878184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4888184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4898184Ssomayeh@cs.wisc.edu } 4908184Ssomayeh@cs.wisc.edu 4918161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4926882SBrad.Beckmann@amd.com 4937550SBrad.Beckmann@amd.com if (accessPhysMem) { 49410525Snilay@cs.wisc.edu ruby_system->getPhysMem()->functionalAccess(pkt); 4958184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4967915SBrad.Beckmann@amd.com pkt->makeResponse(); 4977550SBrad.Beckmann@amd.com } 4986882SBrad.Beckmann@amd.com 4996882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 5006882SBrad.Beckmann@amd.com if (needsResponse) { 5018161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 5029163Sandreas.hansson@arm.com // send next cycle 5039206Snilay@cs.wisc.edu schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 5046882SBrad.Beckmann@amd.com } else { 5056882SBrad.Beckmann@amd.com delete pkt; 5066882SBrad.Beckmann@amd.com } 50710525Snilay@cs.wisc.edu 5088161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 5096882SBrad.Beckmann@amd.com} 5106882SBrad.Beckmann@amd.com 5118922Swilliam.wang@arm.comAddrRangeList 51210090Snilay@cs.wisc.eduRubyPort::PioSlavePort::getAddrRanges() const 5138922Swilliam.wang@arm.com{ 5148922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 5158922Swilliam.wang@arm.com AddrRangeList ranges; 51610090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 51710090Snilay@cs.wisc.edu 51810090Snilay@cs.wisc.edu for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 51910090Snilay@cs.wisc.edu ranges.splice(ranges.begin(), 52010090Snilay@cs.wisc.edu ruby_port->master_ports[i]->getAddrRanges()); 52110090Snilay@cs.wisc.edu } 52210481Sandreas.hansson@arm.com for (const auto M5_VAR_USED &r : ranges) 52310481Sandreas.hansson@arm.com DPRINTF(RubyPort, "%s\n", r.to_string()); 5248922Swilliam.wang@arm.com return ranges; 5258922Swilliam.wang@arm.com} 5268922Swilliam.wang@arm.com 5276882SBrad.Beckmann@amd.combool 52810090Snilay@cs.wisc.eduRubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 5296882SBrad.Beckmann@amd.com{ 53010090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 5318931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 5326882SBrad.Beckmann@amd.com} 5337909Shestness@cs.utexas.edu 5348717Snilay@cs.wisc.eduvoid 5358717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 5368717Snilay@cs.wisc.edu{ 5378717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 5389633Sjthestness@gmail.com // This request is deleted in the stack-allocated packet destructor 5399633Sjthestness@gmail.com // when this function exits 5409633Sjthestness@gmail.com // TODO: should this really be using funcMasterId? 5419633Sjthestness@gmail.com RequestPtr req = 5429633Sjthestness@gmail.com new Request(address.getAddress(), 0, 0, Request::funcMasterId); 5439633Sjthestness@gmail.com // Use a single packet to signal all snooping ports of the invalidation. 5449633Sjthestness@gmail.com // This assumes that snooping ports do NOT modify the packet/request 5459633Sjthestness@gmail.com Packet pkt(req, MemCmd::InvalidationReq); 5468922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 5479088Sandreas.hansson@arm.com // check if the connected master port is snooping 5489088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 5498948Sandreas.hansson@arm.com // send as a snoop request 5509633Sjthestness@gmail.com (*p)->sendTimingSnoopReq(&pkt); 5518922Swilliam.wang@arm.com } 5528717Snilay@cs.wisc.edu } 5538717Snilay@cs.wisc.edu} 55410090Snilay@cs.wisc.edu 55510090Snilay@cs.wisc.eduvoid 55610090Snilay@cs.wisc.eduRubyPort::PioMasterPort::recvRangeChange() 55710090Snilay@cs.wisc.edu{ 55810090Snilay@cs.wisc.edu RubyPort &r = static_cast<RubyPort &>(owner); 55910090Snilay@cs.wisc.edu r.gotAddrRanges--; 56010117Snilay@cs.wisc.edu if (r.gotAddrRanges == 0 && FullSystem) { 56110090Snilay@cs.wisc.edu r.pioSlavePort.sendRangeChange(); 56210090Snilay@cs.wisc.edu } 56310090Snilay@cs.wisc.edu} 564