RubyPort.cc revision 10089
16876Ssteve.reinhardt@amd.com/* 210089Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 498923Sandreas.hansson@arm.com#include "sim/system.hh" 506285Snate@binkert.org 516876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 528922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 538922Swilliam.wang@arm.com m_mandatory_q_ptr(NULL), 548922Swilliam.wang@arm.com pio_port(csprintf("%s-pio-port", name()), this), 5510089Sandreas.hansson@arm.com m_usingRubyTester(p->using_ruby_tester), 569342SAndreas.Sandberg@arm.com drainManager(NULL), ruby_system(p->ruby_system), system(p->system), 5710089Sandreas.hansson@arm.com access_phys_mem(p->access_phys_mem) 586876Ssteve.reinhardt@amd.com{ 596876Ssteve.reinhardt@amd.com assert(m_version != -1); 606876Ssteve.reinhardt@amd.com 618922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 628922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 638922Swilliam.wang@arm.com slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 6410089Sandreas.hansson@arm.com this, ruby_system, 6510089Sandreas.hansson@arm.com access_phys_mem, i)); 668922Swilliam.wang@arm.com } 677039Snate@binkert.org 688922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 698922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 708922Swilliam.wang@arm.com master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 718922Swilliam.wang@arm.com this)); 728922Swilliam.wang@arm.com } 736876Ssteve.reinhardt@amd.com} 746876Ssteve.reinhardt@amd.com 757039Snate@binkert.orgvoid 767039Snate@binkert.orgRubyPort::init() 776882SBrad.Beckmann@amd.com{ 786882SBrad.Beckmann@amd.com assert(m_controller != NULL); 796882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 809508Snilay@cs.wisc.edu m_mandatory_q_ptr->setSender(this); 816882SBrad.Beckmann@amd.com} 826882SBrad.Beckmann@amd.com 839294Sandreas.hansson@arm.comBaseMasterPort & 849294Sandreas.hansson@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 856876Ssteve.reinhardt@amd.com{ 868922Swilliam.wang@arm.com if (if_name == "pio_port") { 878922Swilliam.wang@arm.com return pio_port; 888922Swilliam.wang@arm.com } 898922Swilliam.wang@arm.com 908839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 918839Sandreas.hansson@arm.com // port 928922Swilliam.wang@arm.com if (if_name != "master") { 938922Swilliam.wang@arm.com // pass it along to our super class 948922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 958922Swilliam.wang@arm.com } else { 969294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 978922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 988922Swilliam.wang@arm.com } 998839Sandreas.hansson@arm.com 1008922Swilliam.wang@arm.com return *master_ports[idx]; 1018839Sandreas.hansson@arm.com } 1028922Swilliam.wang@arm.com} 1038839Sandreas.hansson@arm.com 1049294Sandreas.hansson@arm.comBaseSlavePort & 1059294Sandreas.hansson@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 1068922Swilliam.wang@arm.com{ 1078922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1088922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1098922Swilliam.wang@arm.com if (if_name != "slave") { 1108922Swilliam.wang@arm.com // pass it along to our super class 1118922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1128922Swilliam.wang@arm.com } else { 1139294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 1148922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1158922Swilliam.wang@arm.com } 1168922Swilliam.wang@arm.com 1178922Swilliam.wang@arm.com return *slave_ports[idx]; 1187039Snate@binkert.org } 1196876Ssteve.reinhardt@amd.com} 1206882SBrad.Beckmann@amd.com 1217039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1226882SBrad.Beckmann@amd.com RubyPort *_port) 12310089Sandreas.hansson@arm.com : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 12410089Sandreas.hansson@arm.com ruby_port(_port) 1256882SBrad.Beckmann@amd.com{ 1268922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 1276882SBrad.Beckmann@amd.com} 1286882SBrad.Beckmann@amd.com 1298436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 13010089Sandreas.hansson@arm.com RubySystem *_system, bool _access_phys_mem, PortID id) 13110089Sandreas.hansson@arm.com : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 1328914Sandreas.hansson@arm.com ruby_port(_port), ruby_system(_system), 13310089Sandreas.hansson@arm.com access_phys_mem(_access_phys_mem) 1346882SBrad.Beckmann@amd.com{ 1358922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 1366882SBrad.Beckmann@amd.com} 1376882SBrad.Beckmann@amd.com 1386882SBrad.Beckmann@amd.comTick 1396882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1406882SBrad.Beckmann@amd.com{ 1416882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1426882SBrad.Beckmann@amd.com return 0; 1436882SBrad.Beckmann@amd.com} 1446882SBrad.Beckmann@amd.com 14510089Sandreas.hansson@arm.combool 14610089Sandreas.hansson@arm.comRubyPort::recvTimingResp(PacketPtr pkt, PortID master_port_id) 14710089Sandreas.hansson@arm.com{ 14810089Sandreas.hansson@arm.com // got a response from a device 14910089Sandreas.hansson@arm.com assert(pkt->isResponse()); 1506882SBrad.Beckmann@amd.com 1517039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1527039Snate@binkert.org // and it must forward these responses back to the particular CPU. 15310089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Pio response for address %#x, going to %d\n", 15410089Sandreas.hansson@arm.com pkt->getAddr(), pkt->getDest()); 1556882SBrad.Beckmann@amd.com 15610089Sandreas.hansson@arm.com // Retrieve the port from the destination field 15710089Sandreas.hansson@arm.com assert(pkt->getDest() < slave_ports.size()); 1587039Snate@binkert.org 15910089Sandreas.hansson@arm.com // attempt to send the response in the next cycle 16010089Sandreas.hansson@arm.com slave_ports[pkt->getDest()]->schedTimingResp(pkt, curTick() + 16110089Sandreas.hansson@arm.com g_system_ptr->clockPeriod()); 1627039Snate@binkert.org 1636882SBrad.Beckmann@amd.com return true; 1646882SBrad.Beckmann@amd.com} 1656882SBrad.Beckmann@amd.com 1666882SBrad.Beckmann@amd.combool 1678975Sandreas.hansson@arm.comRubyPort::M5Port::recvTimingReq(PacketPtr pkt) 1686882SBrad.Beckmann@amd.com{ 1698161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 17010089Sandreas.hansson@arm.com "Timing access for address %#x on port %d\n", pkt->getAddr(), 17110089Sandreas.hansson@arm.com id); 1726882SBrad.Beckmann@amd.com 1739662Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) 1749662Sandreas.hansson@arm.com panic("RubyPort should never see an inhibited request\n"); 1756882SBrad.Beckmann@amd.com 17610089Sandreas.hansson@arm.com // Save the port id to be used later to route the response 17710089Sandreas.hansson@arm.com pkt->setSrc(id); 1786922SBrad.Beckmann@amd.com 1796882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 1806882SBrad.Beckmann@amd.com // pio port. 1816882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 1828851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 1838161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1846922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 1856922SBrad.Beckmann@amd.com pkt->getAddr()); 1866882SBrad.Beckmann@amd.com 1879163Sandreas.hansson@arm.com // send next cycle 1889206Snilay@cs.wisc.edu ruby_port->pio_port.schedTimingReq(pkt, 1899206Snilay@cs.wisc.edu curTick() + g_system_ptr->clockPeriod()); 1909163Sandreas.hansson@arm.com return true; 1916882SBrad.Beckmann@amd.com } 1926882SBrad.Beckmann@amd.com 1938615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 1948615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 1957906SBrad.Beckmann@amd.com 1966882SBrad.Beckmann@amd.com // Submit the ruby request 1978615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 1987023SBrad.Beckmann@amd.com 1997550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 20010089Sandreas.hansson@arm.com // Otherwise, we need to tell the port to retry at a later point 20110089Sandreas.hansson@arm.com // and return false. 2027550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 20310089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 20410089Sandreas.hansson@arm.com pkt->getAddr()); 2056922SBrad.Beckmann@amd.com return true; 2066882SBrad.Beckmann@amd.com } 2077023SBrad.Beckmann@amd.com 2087910SBrad.Beckmann@amd.com // 2097910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2107910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2117910SBrad.Beckmann@amd.com // 2127910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2137910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2147910SBrad.Beckmann@amd.com } 2157910SBrad.Beckmann@amd.com 2168161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2177906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2187039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2197039Snate@binkert.org 2206922SBrad.Beckmann@amd.com return false; 2216882SBrad.Beckmann@amd.com} 2226882SBrad.Beckmann@amd.com 2238436SBrad.Beckmann@amd.comvoid 2248436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 2258436SBrad.Beckmann@amd.com{ 2268436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 2278436SBrad.Beckmann@amd.com pkt->getAddr()); 2288436SBrad.Beckmann@amd.com 2298436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2308436SBrad.Beckmann@amd.com // pio port. 2318436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 2328851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 2338436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 2348436SBrad.Beckmann@amd.com pkt->getAddr()); 2358436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 2368436SBrad.Beckmann@amd.com } 2378436SBrad.Beckmann@amd.com 2388436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 2398436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 2408436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 2418436SBrad.Beckmann@amd.com 2428436SBrad.Beckmann@amd.com bool accessSucceeded = false; 2438436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 2448436SBrad.Beckmann@amd.com 2458436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 2468436SBrad.Beckmann@amd.com if (pkt->isRead()) { 2479270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalRead(pkt); 2488436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 2499270Snilay@cs.wisc.edu accessSucceeded = ruby_system->functionalWrite(pkt); 2508436SBrad.Beckmann@amd.com } else { 2518436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 2528436SBrad.Beckmann@amd.com pkt->cmdString()); 2538436SBrad.Beckmann@amd.com } 2548436SBrad.Beckmann@amd.com 2558436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 2568436SBrad.Beckmann@amd.com // the functional request failed 2578436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 2588436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 2598436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 2608436SBrad.Beckmann@amd.com } 2618436SBrad.Beckmann@amd.com 2628436SBrad.Beckmann@amd.com if (access_phys_mem) { 2638436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 2648436SBrad.Beckmann@amd.com // The following command performs the real functional access. 2658436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 2668436SBrad.Beckmann@amd.com // of data. 2678931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().functionalAccess(pkt); 2688436SBrad.Beckmann@amd.com } 2698436SBrad.Beckmann@amd.com 2708436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 2718436SBrad.Beckmann@amd.com if (needsResponse) { 2728436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 2738706Sandreas.hansson@arm.com 2748706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 2758706Sandreas.hansson@arm.com // communicated through the packet pointer 2768706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 2778706Sandreas.hansson@arm.com // sendFunctional(pkt); 2788436SBrad.Beckmann@amd.com } 2798436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 2808436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 2818436SBrad.Beckmann@amd.com} 2828436SBrad.Beckmann@amd.com 2836882SBrad.Beckmann@amd.comvoid 2846922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 2856882SBrad.Beckmann@amd.com{ 28610089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 28710089Sandreas.hansson@arm.com pkt->getAddr()); 2887039Snate@binkert.org 28910089Sandreas.hansson@arm.com // The packet was destined for memory and has not yet been turned 29010089Sandreas.hansson@arm.com // into a response 29110089Sandreas.hansson@arm.com assert(system->isMemAddr(pkt->getAddr())); 29210089Sandreas.hansson@arm.com assert(pkt->isRequest()); 2936882SBrad.Beckmann@amd.com 29410089Sandreas.hansson@arm.com // As it has not yet been turned around, the source field tells us 29510089Sandreas.hansson@arm.com // which port it came from. 29610089Sandreas.hansson@arm.com assert(pkt->getSrc() < slave_ports.size()); 29710089Sandreas.hansson@arm.com 29810089Sandreas.hansson@arm.com slave_ports[pkt->getSrc()]->hitCallback(pkt); 2997910SBrad.Beckmann@amd.com 3007910SBrad.Beckmann@amd.com // 3017910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 3027910SBrad.Beckmann@amd.com // likely has free resources now. 3037910SBrad.Beckmann@amd.com // 30410089Sandreas.hansson@arm.com if (!retryList.empty()) { 3058162SBrad.Beckmann@amd.com // 3068162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 3078162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 3088162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 3098162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 3108162SBrad.Beckmann@amd.com // sendRetry. 3118162SBrad.Beckmann@amd.com // 31210089Sandreas.hansson@arm.com std::vector<M5Port*> curRetryList(retryList); 3138162SBrad.Beckmann@amd.com 3148162SBrad.Beckmann@amd.com retryList.clear(); 31510089Sandreas.hansson@arm.com 31610089Sandreas.hansson@arm.com for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 3178162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 3187910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3197910SBrad.Beckmann@amd.com (*i)->name()); 3208162SBrad.Beckmann@amd.com (*i)->sendRetry(); 3217910SBrad.Beckmann@amd.com } 3227910SBrad.Beckmann@amd.com } 3238688Snilay@cs.wisc.edu 3248688Snilay@cs.wisc.edu testDrainComplete(); 3258688Snilay@cs.wisc.edu} 3268688Snilay@cs.wisc.edu 3278688Snilay@cs.wisc.eduvoid 3288688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 3298688Snilay@cs.wisc.edu{ 3308688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 3319342SAndreas.Sandberg@arm.com if (drainManager != NULL) { 3329245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 3339152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 3348688Snilay@cs.wisc.edu if (drainCount == 0) { 3359342SAndreas.Sandberg@arm.com DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 3369342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 3379342SAndreas.Sandberg@arm.com // Clear the drain manager once we're done with it. 3389342SAndreas.Sandberg@arm.com drainManager = NULL; 3398688Snilay@cs.wisc.edu } 3408688Snilay@cs.wisc.edu } 3418688Snilay@cs.wisc.edu} 3428688Snilay@cs.wisc.edu 3438688Snilay@cs.wisc.eduunsigned int 3449342SAndreas.Sandberg@arm.comRubyPort::getChildDrainCount(DrainManager *dm) 3458688Snilay@cs.wisc.edu{ 3468688Snilay@cs.wisc.edu int count = 0; 3478688Snilay@cs.wisc.edu 3488851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 3499342SAndreas.Sandberg@arm.com count += pio_port.drain(dm); 3508688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 3518688Snilay@cs.wisc.edu } 3528688Snilay@cs.wisc.edu 3538922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 3549342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3558922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 3568922Swilliam.wang@arm.com } 3578922Swilliam.wang@arm.com 3588922Swilliam.wang@arm.com for (std::vector<PioPort*>::iterator p = master_ports.begin(); 3598922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 3609342SAndreas.Sandberg@arm.com count += (*p)->drain(dm); 3618922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 3628688Snilay@cs.wisc.edu } 3638688Snilay@cs.wisc.edu 3648688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 3658688Snilay@cs.wisc.edu 3668688Snilay@cs.wisc.edu return count; 3678688Snilay@cs.wisc.edu} 3688688Snilay@cs.wisc.edu 3698688Snilay@cs.wisc.eduunsigned int 3709342SAndreas.Sandberg@arm.comRubyPort::drain(DrainManager *dm) 3718688Snilay@cs.wisc.edu{ 3728688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 3738688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 3748688Snilay@cs.wisc.edu } 3758688Snilay@cs.wisc.edu 3769245Shestness@cs.wisc.edu // 3779245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 3789342SAndreas.Sandberg@arm.com // requests before it should call drainManager->signalDrainDone() 3799245Shestness@cs.wisc.edu // 3809245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 3819245Shestness@cs.wisc.edu bool need_drain = outstandingCount() > 0; 3829245Shestness@cs.wisc.edu 3839245Shestness@cs.wisc.edu // 3849245Shestness@cs.wisc.edu // Also, get the number of child ports that will also need to clear 3859342SAndreas.Sandberg@arm.com // their buffered requests before they call drainManager->signalDrainDone() 3869245Shestness@cs.wisc.edu // 3879342SAndreas.Sandberg@arm.com unsigned int child_drain_count = getChildDrainCount(dm); 3888688Snilay@cs.wisc.edu 3898688Snilay@cs.wisc.edu // Set status 3909245Shestness@cs.wisc.edu if (need_drain) { 3919342SAndreas.Sandberg@arm.com drainManager = dm; 3928688Snilay@cs.wisc.edu 3939152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 3949342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 3959245Shestness@cs.wisc.edu return child_drain_count + 1; 3968688Snilay@cs.wisc.edu } 3978688Snilay@cs.wisc.edu 3989342SAndreas.Sandberg@arm.com drainManager = NULL; 3999342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 4009245Shestness@cs.wisc.edu return child_drain_count; 4016882SBrad.Beckmann@amd.com} 4026882SBrad.Beckmann@amd.com 4036882SBrad.Beckmann@amd.comvoid 4046882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 4056882SBrad.Beckmann@amd.com{ 4066882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4076882SBrad.Beckmann@amd.com 4087550SBrad.Beckmann@amd.com // 4097915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 4108184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 4117550SBrad.Beckmann@amd.com // 4127915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 4137550SBrad.Beckmann@amd.com 4147550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4157550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4167550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4177550SBrad.Beckmann@amd.com // 4187550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4197550SBrad.Beckmann@amd.com // 4207550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4217550SBrad.Beckmann@amd.com } else { 4227550SBrad.Beckmann@amd.com // 4237550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4247550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4257550SBrad.Beckmann@amd.com // 4267550SBrad.Beckmann@amd.com accessPhysMem = false; 4277550SBrad.Beckmann@amd.com } 4287550SBrad.Beckmann@amd.com } else { 4297550SBrad.Beckmann@amd.com // 4307550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4317550SBrad.Beckmann@amd.com // not lock the blocks. 4327550SBrad.Beckmann@amd.com // 4337550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4347550SBrad.Beckmann@amd.com } 4357550SBrad.Beckmann@amd.com } 4368184Ssomayeh@cs.wisc.edu 4378184Ssomayeh@cs.wisc.edu // 4388184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4398184Ssomayeh@cs.wisc.edu // 4408184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4418184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4428184Ssomayeh@cs.wisc.edu } 4438184Ssomayeh@cs.wisc.edu 4448161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4456882SBrad.Beckmann@amd.com 4467550SBrad.Beckmann@amd.com if (accessPhysMem) { 4478931Sandreas.hansson@arm.com ruby_port->system->getPhysMem().access(pkt); 4488184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4497915SBrad.Beckmann@amd.com pkt->makeResponse(); 4507550SBrad.Beckmann@amd.com } 4516882SBrad.Beckmann@amd.com 4526882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4536882SBrad.Beckmann@amd.com if (needsResponse) { 4548161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 4559163Sandreas.hansson@arm.com // send next cycle 4569206Snilay@cs.wisc.edu schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 4576882SBrad.Beckmann@amd.com } else { 4586882SBrad.Beckmann@amd.com delete pkt; 4596882SBrad.Beckmann@amd.com } 4608161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 4616882SBrad.Beckmann@amd.com} 4626882SBrad.Beckmann@amd.com 4638922Swilliam.wang@arm.comAddrRangeList 4649090Sandreas.hansson@arm.comRubyPort::M5Port::getAddrRanges() const 4658922Swilliam.wang@arm.com{ 4668922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 4678922Swilliam.wang@arm.com AddrRangeList ranges; 4688922Swilliam.wang@arm.com return ranges; 4698922Swilliam.wang@arm.com} 4708922Swilliam.wang@arm.com 4716882SBrad.Beckmann@amd.combool 47210089Sandreas.hansson@arm.comRubyPort::M5Port::isPhysMemAddress(Addr addr) const 4736882SBrad.Beckmann@amd.com{ 4748931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 4756882SBrad.Beckmann@amd.com} 4767909Shestness@cs.utexas.edu 4778717Snilay@cs.wisc.eduvoid 4788717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 4798717Snilay@cs.wisc.edu{ 4808717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 4819633Sjthestness@gmail.com // This request is deleted in the stack-allocated packet destructor 4829633Sjthestness@gmail.com // when this function exits 4839633Sjthestness@gmail.com // TODO: should this really be using funcMasterId? 4849633Sjthestness@gmail.com RequestPtr req = 4859633Sjthestness@gmail.com new Request(address.getAddress(), 0, 0, Request::funcMasterId); 4869633Sjthestness@gmail.com // Use a single packet to signal all snooping ports of the invalidation. 4879633Sjthestness@gmail.com // This assumes that snooping ports do NOT modify the packet/request 4889633Sjthestness@gmail.com Packet pkt(req, MemCmd::InvalidationReq); 4898922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 4909088Sandreas.hansson@arm.com // check if the connected master port is snooping 4919088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 4928948Sandreas.hansson@arm.com // send as a snoop request 4939633Sjthestness@gmail.com (*p)->sendTimingSnoopReq(&pkt); 4948922Swilliam.wang@arm.com } 4958717Snilay@cs.wisc.edu } 4968717Snilay@cs.wisc.edu} 497