PerfectCacheMemory.hh revision 6145 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * PerfectCacheMemory.h
32 *
33 * Description:
34 *
35 * $Id$
36 *
37 */
38
39#ifndef PERFECTCACHEMEMORY_H
40#define PERFECTCACHEMEMORY_H
41
42#include "Global.hh"
43#include "Map.hh"
44#include "AccessPermission.hh"
45#include "RubyConfig.hh"
46#include "Address.hh"
47#include "interface.hh"
48#include "AbstractChip.hh"
49
50template<class ENTRY>
51class PerfectCacheLineState {
52public:
53  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
54  AccessPermission m_permission;
55  ENTRY m_entry;
56};
57
58template<class ENTRY>
59class PerfectCacheMemory {
60public:
61
62  // Constructors
63  PerfectCacheMemory(AbstractChip* chip_ptr);
64
65  // Destructor
66  //~PerfectCacheMemory();
67
68  // Public Methods
69
70  static void printConfig(ostream& out);
71
72  // perform a cache access and see if we hit or not.  Return true on
73  // a hit.
74  bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
75
76  // tests to see if an address is present in the cache
77  bool isTagPresent(const Address& address) const;
78
79  // Returns true if there is:
80  //   a) a tag match on this address or there is
81  //   b) an Invalid line in the same cache "way"
82  bool cacheAvail(const Address& address) const;
83
84  // find an Invalid entry and sets the tag appropriate for the address
85  void allocate(const Address& address);
86
87  void deallocate(const Address& address);
88
89  // Returns with the physical address of the conflicting cache line
90  Address cacheProbe(const Address& newAddress) const;
91
92  // looks an address up in the cache
93  ENTRY& lookup(const Address& address);
94  const ENTRY& lookup(const Address& address) const;
95
96  // Get/Set permission of cache block
97  AccessPermission getPermission(const Address& address) const;
98  void changePermission(const Address& address, AccessPermission new_perm);
99
100  // Print cache contents
101  void print(ostream& out) const;
102private:
103  // Private Methods
104
105  // Private copy constructor and assignment operator
106  PerfectCacheMemory(const PerfectCacheMemory& obj);
107  PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
108
109  // Data Members (m_prefix)
110  Map<Address, PerfectCacheLineState<ENTRY> > m_map;
111  AbstractChip* m_chip_ptr;
112};
113
114// Output operator declaration
115//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
116
117// ******************* Definitions *******************
118
119// Output operator definition
120template<class ENTRY>
121extern inline
122ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
123{
124  obj.print(out);
125  out << flush;
126  return out;
127}
128
129
130// ****************************************************************
131
132template<class ENTRY>
133extern inline
134PerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr)
135{
136  m_chip_ptr = chip_ptr;
137}
138
139// STATIC METHODS
140
141template<class ENTRY>
142extern inline
143void PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
144{
145}
146
147// PUBLIC METHODS
148
149template<class ENTRY>
150extern inline
151bool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
152{
153  ERROR_MSG("not implemented");
154}
155
156// tests to see if an address is present in the cache
157template<class ENTRY>
158extern inline
159bool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
160{
161  return m_map.exist(line_address(address));
162}
163
164template<class ENTRY>
165extern inline
166bool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
167{
168  return true;
169}
170
171// find an Invalid or already allocated entry and sets the tag
172// appropriate for the address
173template<class ENTRY>
174extern inline
175void PerfectCacheMemory<ENTRY>::allocate(const Address& address)
176{
177  PerfectCacheLineState<ENTRY> line_state;
178  line_state.m_permission = AccessPermission_Busy;
179  line_state.m_entry = ENTRY();
180  m_map.add(line_address(address), line_state);
181}
182
183// deallocate entry
184template<class ENTRY>
185extern inline
186void PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
187{
188  m_map.erase(line_address(address));
189}
190
191// Returns with the physical address of the conflicting cache line
192template<class ENTRY>
193extern inline
194Address PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
195{
196  ERROR_MSG("cacheProbe called in perfect cache");
197}
198
199// looks an address up in the cache
200template<class ENTRY>
201extern inline
202ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
203{
204  return m_map.lookup(line_address(address)).m_entry;
205}
206
207// looks an address up in the cache
208template<class ENTRY>
209extern inline
210const ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
211{
212  return m_map.lookup(line_address(address)).m_entry;
213}
214
215template<class ENTRY>
216extern inline
217AccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
218{
219  return m_map.lookup(line_address(address)).m_permission;
220}
221
222template<class ENTRY>
223extern inline
224void PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
225{
226  Address line_address = address;
227  line_address.makeLineAddress();
228  PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
229  AccessPermission old_perm = line_state.m_permission;
230  line_state.m_permission = new_perm;
231}
232
233template<class ENTRY>
234extern inline
235void PerfectCacheMemory<ENTRY>::print(ostream& out) const
236{
237}
238
239#endif //PERFECTCACHEMEMORY_H
240