CacheMemory.hh revision 7039 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
31
32#include <vector>
33
34#include "base/hashmap.hh"
35#include "mem/gems_common/Vector.hh"
36#include "mem/protocol/AccessPermission.hh"
37#include "mem/protocol/CacheMsg.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/MachineType.hh"
40#include "mem/ruby/common/Address.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/common/Global.hh"
43#include "mem/ruby/profiler/CacheProfiler.hh"
44#include "mem/ruby/recorder/CacheRecorder.hh"
45#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
46#include "mem/ruby/slicc_interface/AbstractController.hh"
47#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
48#include "mem/ruby/system/LRUPolicy.hh"
49#include "mem/ruby/system/PseudoLRUPolicy.hh"
50#include "mem/ruby/system/System.hh"
51#include "params/RubyCache.hh"
52#include "sim/sim_object.hh"
53
54class CacheMemory : public SimObject
55{
56  public:
57    typedef RubyCacheParams Params;
58    CacheMemory(const Params *p);
59    ~CacheMemory();
60
61    void init();
62
63    // Public Methods
64    void printConfig(ostream& out);
65
66    // perform a cache access and see if we hit or not.  Return true on a hit.
67    bool tryCacheAccess(const Address& address, CacheRequestType type,
68                        DataBlock*& data_ptr);
69
70    // similar to above, but doesn't require full access check
71    bool testCacheAccess(const Address& address, CacheRequestType type,
72                         DataBlock*& data_ptr);
73
74    // tests to see if an address is present in the cache
75    bool isTagPresent(const Address& address) const;
76
77    // Returns true if there is:
78    //   a) a tag match on this address or there is
79    //   b) an unused line in the same cache "way"
80    bool cacheAvail(const Address& address) const;
81
82    // find an unused entry and sets the tag appropriate for the address
83    void allocate(const Address& address, AbstractCacheEntry* new_entry);
84
85    // Explicitly free up this address
86    void deallocate(const Address& address);
87
88    // Returns with the physical address of the conflicting cache line
89    Address cacheProbe(const Address& address) const;
90
91    // looks an address up in the cache
92    AbstractCacheEntry& lookup(const Address& address);
93    const AbstractCacheEntry& lookup(const Address& address) const;
94
95    // Get/Set permission of cache block
96    AccessPermission getPermission(const Address& address) const;
97    void changePermission(const Address& address, AccessPermission new_perm);
98
99    int getLatency() const { return m_latency; }
100
101    // Hook for checkpointing the contents of the cache
102    void recordCacheContents(CacheRecorder& tr) const;
103    void
104    setAsInstructionCache(bool is_icache)
105    {
106        m_is_instruction_only_cache = is_icache;
107    }
108
109    // Set this address to most recently used
110    void setMRU(const Address& address);
111
112    void profileMiss(const CacheMsg & msg);
113
114    void getMemoryValue(const Address& addr, char* value,
115                        unsigned int size_in_bytes);
116    void setMemoryValue(const Address& addr, char* value,
117                        unsigned int size_in_bytes);
118
119    void setLocked (const Address& addr, int context);
120    void clearLocked (const Address& addr);
121    bool isLocked (const Address& addr, int context);
122    // Print cache contents
123    void print(ostream& out) const;
124    void printData(ostream& out) const;
125
126    void clearStats() const;
127    void printStats(ostream& out) const;
128
129  private:
130    // convert a Address to its location in the cache
131    Index addressToCacheSet(const Address& address) const;
132
133    // Given a cache tag: returns the index of the tag in a set.
134    // returns -1 if the tag is not found.
135    int findTagInSet(Index line, const Address& tag) const;
136    int findTagInSetIgnorePermissions(Index cacheSet,
137                                      const Address& tag) const;
138
139    // Private copy constructor and assignment operator
140    CacheMemory(const CacheMemory& obj);
141    CacheMemory& operator=(const CacheMemory& obj);
142
143  private:
144    const string m_cache_name;
145    int m_latency;
146
147    // Data Members (m_prefix)
148    bool m_is_instruction_only_cache;
149    bool m_is_data_only_cache;
150
151    // The first index is the # of cache lines.
152    // The second index is the the amount associativity.
153    m5::hash_map<Address, int> m_tag_index;
154    Vector<Vector<AbstractCacheEntry*> > m_cache;
155    Vector<Vector<int> > m_locked;
156
157    AbstractReplacementPolicy *m_replacementPolicy_ptr;
158
159    CacheProfiler* m_profiler_ptr;
160
161    int m_cache_size;
162    string m_policy;
163    int m_cache_num_sets;
164    int m_cache_num_set_bits;
165    int m_cache_assoc;
166};
167
168#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
169
170