CacheMemory.hh revision 9554 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
31
32#include <string>
33#include <vector>
34
35#include "base/hashmap.hh"
36#include "base/statistics.hh"
37#include "mem/protocol/CacheResourceType.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/GenericRequestType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/profiler/CacheProfiler.hh"
43#include "mem/ruby/recorder/CacheRecorder.hh"
44#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
45#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
46#include "mem/ruby/system/BankedArray.hh"
47#include "mem/ruby/system/LRUPolicy.hh"
48#include "mem/ruby/system/PseudoLRUPolicy.hh"
49#include "params/RubyCache.hh"
50#include "sim/sim_object.hh"
51
52class CacheMemory : public SimObject
53{
54  public:
55    typedef RubyCacheParams Params;
56    CacheMemory(const Params *p);
57    ~CacheMemory();
58
59    void init();
60
61    // Public Methods
62    // perform a cache access and see if we hit or not.  Return true on a hit.
63    bool tryCacheAccess(const Address& address, RubyRequestType type,
64                        DataBlock*& data_ptr);
65
66    // similar to above, but doesn't require full access check
67    bool testCacheAccess(const Address& address, RubyRequestType type,
68                         DataBlock*& data_ptr);
69
70    // tests to see if an address is present in the cache
71    bool isTagPresent(const Address& address) const;
72
73    // Returns true if there is:
74    //   a) a tag match on this address or there is
75    //   b) an unused line in the same cache "way"
76    bool cacheAvail(const Address& address) const;
77
78    // find an unused entry and sets the tag appropriate for the address
79    AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
80    void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
81    {
82        allocate(address, new_entry);
83    }
84
85    // Explicitly free up this address
86    void deallocate(const Address& address);
87
88    // Returns with the physical address of the conflicting cache line
89    Address cacheProbe(const Address& address) const;
90
91    // looks an address up in the cache
92    AbstractCacheEntry* lookup(const Address& address);
93    const AbstractCacheEntry* lookup(const Address& address) const;
94
95    Cycles getLatency() const { return m_latency; }
96
97    // Hook for checkpointing the contents of the cache
98    void recordCacheContents(int cntrl, CacheRecorder* tr) const;
99
100    // Set this address to most recently used
101    void setMRU(const Address& address);
102
103    void profileMiss(const RubyRequest & msg);
104
105    void profileGenericRequest(GenericRequestType requestType,
106                               RubyAccessMode accessType,
107                               PrefetchBit pfBit);
108
109    void setLocked (const Address& addr, int context);
110    void clearLocked (const Address& addr);
111    bool isLocked (const Address& addr, int context);
112    // Print cache contents
113    void print(std::ostream& out) const;
114    void printData(std::ostream& out) const;
115
116    void clearStats() const;
117    void printStats(std::ostream& out) const;
118
119    void recordRequestType(CacheRequestType requestType);
120    void regStats();
121
122    Stats::Scalar numDataArrayReads;
123    Stats::Scalar numDataArrayWrites;
124    Stats::Scalar numTagArrayReads;
125    Stats::Scalar numTagArrayWrites;
126
127    bool checkResourceAvailable(CacheResourceType res, Address addr);
128
129    Stats::Scalar numTagArrayStalls;
130    Stats::Scalar numDataArrayStalls;
131  private:
132    // convert a Address to its location in the cache
133    Index addressToCacheSet(const Address& address) const;
134
135    // Given a cache tag: returns the index of the tag in a set.
136    // returns -1 if the tag is not found.
137    int findTagInSet(Index line, const Address& tag) const;
138    int findTagInSetIgnorePermissions(Index cacheSet,
139                                      const Address& tag) const;
140
141    // Private copy constructor and assignment operator
142    CacheMemory(const CacheMemory& obj);
143    CacheMemory& operator=(const CacheMemory& obj);
144
145  private:
146    const std::string m_cache_name;
147    Cycles m_latency;
148
149    // Data Members (m_prefix)
150    bool m_is_instruction_only_cache;
151
152    // The first index is the # of cache lines.
153    // The second index is the the amount associativity.
154    m5::hash_map<Address, int> m_tag_index;
155    std::vector<std::vector<AbstractCacheEntry*> > m_cache;
156
157    AbstractReplacementPolicy *m_replacementPolicy_ptr;
158
159    CacheProfiler* m_profiler_ptr;
160
161    BankedArray dataArray;
162    BankedArray tagArray;
163
164    int m_cache_size;
165    std::string m_policy;
166    int m_cache_num_sets;
167    int m_cache_num_set_bits;
168    int m_cache_assoc;
169    int m_start_index_bit;
170    bool m_resource_stalls;
171};
172
173std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
174
175#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
176