CacheMemory.hh revision 9105
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com */ 2810259SAndrew.Bardsley@arm.com 2910259SAndrew.Bardsley@arm.com#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 3010259SAndrew.Bardsley@arm.com#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#include <iostream> 3310259SAndrew.Bardsley@arm.com#include <string> 3410259SAndrew.Bardsley@arm.com#include <vector> 3510259SAndrew.Bardsley@arm.com 3610259SAndrew.Bardsley@arm.com#include "base/hashmap.hh" 3710259SAndrew.Bardsley@arm.com#include "base/statistics.hh" 3810259SAndrew.Bardsley@arm.com#include "mem/protocol/CacheResourceType.hh" 3910259SAndrew.Bardsley@arm.com#include "mem/protocol/CacheRequestType.hh" 4011793Sbrandon.potter@amd.com#include "mem/protocol/GenericRequestType.hh" 4111793Sbrandon.potter@amd.com#include "mem/protocol/RubyRequest.hh" 4210259SAndrew.Bardsley@arm.com#include "mem/ruby/common/DataBlock.hh" 4310259SAndrew.Bardsley@arm.com#include "mem/ruby/profiler/CacheProfiler.hh" 4410259SAndrew.Bardsley@arm.com#include "mem/ruby/recorder/CacheRecorder.hh" 4510259SAndrew.Bardsley@arm.com#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 4610259SAndrew.Bardsley@arm.com#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4710259SAndrew.Bardsley@arm.com#include "mem/ruby/system/BankedArray.hh" 4810259SAndrew.Bardsley@arm.com#include "mem/ruby/system/LRUPolicy.hh" 4910259SAndrew.Bardsley@arm.com#include "mem/ruby/system/PseudoLRUPolicy.hh" 5010259SAndrew.Bardsley@arm.com#include "params/RubyCache.hh" 5110259SAndrew.Bardsley@arm.com#include "sim/sim_object.hh" 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comclass CacheMemory : public SimObject 5410259SAndrew.Bardsley@arm.com{ 5510259SAndrew.Bardsley@arm.com public: 5610259SAndrew.Bardsley@arm.com typedef RubyCacheParams Params; 5710259SAndrew.Bardsley@arm.com CacheMemory(const Params *p); 5810259SAndrew.Bardsley@arm.com ~CacheMemory(); 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com void init(); 6111567Smitch.hayenga@arm.com 6210259SAndrew.Bardsley@arm.com // Public Methods 6310259SAndrew.Bardsley@arm.com void printConfig(std::ostream& out); 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.com // perform a cache access and see if we hit or not. Return true on a hit. 6610259SAndrew.Bardsley@arm.com bool tryCacheAccess(const Address& address, RubyRequestType type, 6710259SAndrew.Bardsley@arm.com DataBlock*& data_ptr); 6810259SAndrew.Bardsley@arm.com 6910259SAndrew.Bardsley@arm.com // similar to above, but doesn't require full access check 7010259SAndrew.Bardsley@arm.com bool testCacheAccess(const Address& address, RubyRequestType type, 7110259SAndrew.Bardsley@arm.com DataBlock*& data_ptr); 7211567Smitch.hayenga@arm.com 7311567Smitch.hayenga@arm.com // tests to see if an address is present in the cache 7410259SAndrew.Bardsley@arm.com bool isTagPresent(const Address& address) const; 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com // Returns true if there is: 7710259SAndrew.Bardsley@arm.com // a) a tag match on this address or there is 7810259SAndrew.Bardsley@arm.com // b) an unused line in the same cache "way" 7910259SAndrew.Bardsley@arm.com bool cacheAvail(const Address& address) const; 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com // find an unused entry and sets the tag appropriate for the address 8210259SAndrew.Bardsley@arm.com AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry); 8310259SAndrew.Bardsley@arm.com void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 8410259SAndrew.Bardsley@arm.com { 8510259SAndrew.Bardsley@arm.com allocate(address, new_entry); 8610259SAndrew.Bardsley@arm.com } 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com // Explicitly free up this address 8910259SAndrew.Bardsley@arm.com void deallocate(const Address& address); 9010259SAndrew.Bardsley@arm.com 9110259SAndrew.Bardsley@arm.com // Returns with the physical address of the conflicting cache line 9210259SAndrew.Bardsley@arm.com Address cacheProbe(const Address& address) const; 9310259SAndrew.Bardsley@arm.com 9410259SAndrew.Bardsley@arm.com // looks an address up in the cache 9510259SAndrew.Bardsley@arm.com AbstractCacheEntry* lookup(const Address& address); 9610259SAndrew.Bardsley@arm.com const AbstractCacheEntry* lookup(const Address& address) const; 9710259SAndrew.Bardsley@arm.com 9810259SAndrew.Bardsley@arm.com int getLatency() const { return m_latency; } 9910259SAndrew.Bardsley@arm.com 10010259SAndrew.Bardsley@arm.com // Hook for checkpointing the contents of the cache 10110259SAndrew.Bardsley@arm.com void recordCacheContents(int cntrl, CacheRecorder* tr) const; 10210259SAndrew.Bardsley@arm.com 10310259SAndrew.Bardsley@arm.com // Set this address to most recently used 10410259SAndrew.Bardsley@arm.com void setMRU(const Address& address); 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com void profileMiss(const RubyRequest & msg); 10710259SAndrew.Bardsley@arm.com 10810259SAndrew.Bardsley@arm.com void profileGenericRequest(GenericRequestType requestType, 10910259SAndrew.Bardsley@arm.com RubyAccessMode accessType, 11010259SAndrew.Bardsley@arm.com PrefetchBit pfBit); 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.com void setLocked (const Address& addr, int context); 11310259SAndrew.Bardsley@arm.com void clearLocked (const Address& addr); 11410259SAndrew.Bardsley@arm.com bool isLocked (const Address& addr, int context); 11511567Smitch.hayenga@arm.com // Print cache contents 11611567Smitch.hayenga@arm.com void print(std::ostream& out) const; 11711567Smitch.hayenga@arm.com void printData(std::ostream& out) const; 11811567Smitch.hayenga@arm.com 11911567Smitch.hayenga@arm.com void clearStats() const; 12011567Smitch.hayenga@arm.com void printStats(std::ostream& out) const; 12111567Smitch.hayenga@arm.com 12211567Smitch.hayenga@arm.com void recordRequestType(CacheRequestType requestType); 12311567Smitch.hayenga@arm.com void regStats(); 12411567Smitch.hayenga@arm.com 12511567Smitch.hayenga@arm.com Stats::Scalar numDataArrayReads; 12611567Smitch.hayenga@arm.com Stats::Scalar numDataArrayWrites; 12711567Smitch.hayenga@arm.com Stats::Scalar numTagArrayReads; 12811567Smitch.hayenga@arm.com Stats::Scalar numTagArrayWrites; 12911567Smitch.hayenga@arm.com 13011567Smitch.hayenga@arm.com bool checkResourceAvailable(CacheResourceType res, Address addr); 13111567Smitch.hayenga@arm.com 13211567Smitch.hayenga@arm.com Stats::Scalar numTagArrayStalls; 13311567Smitch.hayenga@arm.com Stats::Scalar numDataArrayStalls; 13411567Smitch.hayenga@arm.com private: 13511567Smitch.hayenga@arm.com // convert a Address to its location in the cache 13611567Smitch.hayenga@arm.com Index addressToCacheSet(const Address& address) const; 13711567Smitch.hayenga@arm.com 13811567Smitch.hayenga@arm.com // Given a cache tag: returns the index of the tag in a set. 13911567Smitch.hayenga@arm.com // returns -1 if the tag is not found. 14011567Smitch.hayenga@arm.com int findTagInSet(Index line, const Address& tag) const; 14111567Smitch.hayenga@arm.com int findTagInSetIgnorePermissions(Index cacheSet, 14211567Smitch.hayenga@arm.com const Address& tag) const; 14311567Smitch.hayenga@arm.com 14411567Smitch.hayenga@arm.com // Private copy constructor and assignment operator 14511567Smitch.hayenga@arm.com CacheMemory(const CacheMemory& obj); 14611567Smitch.hayenga@arm.com CacheMemory& operator=(const CacheMemory& obj); 14710259SAndrew.Bardsley@arm.com 14811567Smitch.hayenga@arm.com private: 14910259SAndrew.Bardsley@arm.com const std::string m_cache_name; 15011567Smitch.hayenga@arm.com int m_latency; 15111567Smitch.hayenga@arm.com 15211567Smitch.hayenga@arm.com // Data Members (m_prefix) 15310259SAndrew.Bardsley@arm.com bool m_is_instruction_only_cache; 15410259SAndrew.Bardsley@arm.com 15510259SAndrew.Bardsley@arm.com // The first index is the # of cache lines. 15611567Smitch.hayenga@arm.com // The second index is the the amount associativity. 15710259SAndrew.Bardsley@arm.com m5::hash_map<Address, int> m_tag_index; 15810259SAndrew.Bardsley@arm.com std::vector<std::vector<AbstractCacheEntry*> > m_cache; 15910259SAndrew.Bardsley@arm.com 16010259SAndrew.Bardsley@arm.com AbstractReplacementPolicy *m_replacementPolicy_ptr; 16111567Smitch.hayenga@arm.com 16211567Smitch.hayenga@arm.com CacheProfiler* m_profiler_ptr; 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com BankedArray dataArray; 16511567Smitch.hayenga@arm.com BankedArray tagArray; 16610259SAndrew.Bardsley@arm.com 16710259SAndrew.Bardsley@arm.com int m_cache_size; 16810259SAndrew.Bardsley@arm.com std::string m_policy; 16911567Smitch.hayenga@arm.com int m_cache_num_sets; 17010259SAndrew.Bardsley@arm.com int m_cache_num_set_bits; 17112749Sgiacomo.travaglini@arm.com int m_cache_assoc; 17212749Sgiacomo.travaglini@arm.com int m_start_index_bit; 17310259SAndrew.Bardsley@arm.com bool m_resource_stalls; 17410259SAndrew.Bardsley@arm.com}; 17511567Smitch.hayenga@arm.com 17610259SAndrew.Bardsley@arm.com#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 17710259SAndrew.Bardsley@arm.com 17810259SAndrew.Bardsley@arm.com