CacheMemory.hh revision 8683 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
31
32#include <iostream>
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "mem/protocol/GenericRequestType.hh"
38#include "mem/protocol/RubyRequest.hh"
39#include "mem/ruby/common/DataBlock.hh"
40#include "mem/ruby/profiler/CacheProfiler.hh"
41#include "mem/ruby/recorder/CacheRecorder.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/system/LRUPolicy.hh"
45#include "mem/ruby/system/PseudoLRUPolicy.hh"
46#include "params/RubyCache.hh"
47#include "sim/sim_object.hh"
48
49class CacheMemory : public SimObject
50{
51  public:
52    typedef RubyCacheParams Params;
53    CacheMemory(const Params *p);
54    ~CacheMemory();
55
56    void init();
57
58    // Public Methods
59    void printConfig(std::ostream& out);
60
61    // perform a cache access and see if we hit or not.  Return true on a hit.
62    bool tryCacheAccess(const Address& address, RubyRequestType type,
63                        DataBlock*& data_ptr);
64
65    // similar to above, but doesn't require full access check
66    bool testCacheAccess(const Address& address, RubyRequestType type,
67                         DataBlock*& data_ptr);
68
69    // tests to see if an address is present in the cache
70    bool isTagPresent(const Address& address) const;
71
72    // Returns true if there is:
73    //   a) a tag match on this address or there is
74    //   b) an unused line in the same cache "way"
75    bool cacheAvail(const Address& address) const;
76
77    // find an unused entry and sets the tag appropriate for the address
78    AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
79    void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
80    {
81        allocate(address, new_entry);
82    }
83
84    // Explicitly free up this address
85    void deallocate(const Address& address);
86
87    // Returns with the physical address of the conflicting cache line
88    Address cacheProbe(const Address& address) const;
89
90    // looks an address up in the cache
91    AbstractCacheEntry* lookup(const Address& address);
92    const AbstractCacheEntry* lookup(const Address& address) const;
93
94    int getLatency() const { return m_latency; }
95
96    // Hook for checkpointing the contents of the cache
97    void recordCacheContents(int cntrl, CacheRecorder* tr) const;
98
99    // Set this address to most recently used
100    void setMRU(const Address& address);
101
102    void profileMiss(const RubyRequest & msg);
103
104    void profileGenericRequest(GenericRequestType requestType,
105                               RubyAccessMode accessType,
106                               PrefetchBit pfBit);
107
108    void setLocked (const Address& addr, int context);
109    void clearLocked (const Address& addr);
110    bool isLocked (const Address& addr, int context);
111    // Print cache contents
112    void print(std::ostream& out) const;
113    void printData(std::ostream& out) const;
114
115    void clearStats() const;
116    void printStats(std::ostream& out) const;
117
118  private:
119    // convert a Address to its location in the cache
120    Index addressToCacheSet(const Address& address) const;
121
122    // Given a cache tag: returns the index of the tag in a set.
123    // returns -1 if the tag is not found.
124    int findTagInSet(Index line, const Address& tag) const;
125    int findTagInSetIgnorePermissions(Index cacheSet,
126                                      const Address& tag) const;
127
128    // Private copy constructor and assignment operator
129    CacheMemory(const CacheMemory& obj);
130    CacheMemory& operator=(const CacheMemory& obj);
131
132  private:
133    const std::string m_cache_name;
134    int m_latency;
135
136    // Data Members (m_prefix)
137    bool m_is_instruction_only_cache;
138
139    // The first index is the # of cache lines.
140    // The second index is the the amount associativity.
141    m5::hash_map<Address, int> m_tag_index;
142    std::vector<std::vector<AbstractCacheEntry*> > m_cache;
143
144    AbstractReplacementPolicy *m_replacementPolicy_ptr;
145
146    CacheProfiler* m_profiler_ptr;
147
148    int m_cache_size;
149    std::string m_policy;
150    int m_cache_num_sets;
151    int m_cache_num_set_bits;
152    int m_cache_assoc;
153    int m_start_index_bit;
154};
155
156#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
157
158