CacheMemory.hh revision 7055
12497SN/A/* 210719SMarco.Balboni@ARM.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * Redistribution and use in source and binary forms, with or without 68711SN/A * modification, are permitted provided that the following conditions are 78711SN/A * met: redistributions of source code must retain the above copyright 88711SN/A * notice, this list of conditions and the following disclaimer; 98711SN/A * redistributions in binary form must reproduce the above copyright 108711SN/A * notice, this list of conditions and the following disclaimer in the 118711SN/A * documentation and/or other materials provided with the distribution; 128711SN/A * neither the name of the copyright holders nor the names of its 138711SN/A * contributors may be used to endorse or promote products derived from 142497SN/A * this software without specific prior written permission. 152497SN/A * 162497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272497SN/A */ 282497SN/A 292497SN/A#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 302497SN/A#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 312497SN/A 322497SN/A#include <iostream> 332497SN/A#include <string> 342497SN/A#include <vector> 352497SN/A 362497SN/A#include "base/hashmap.hh" 372497SN/A#include "mem/gems_common/Vector.hh" 382497SN/A#include "mem/protocol/AccessPermission.hh" 392665SN/A#include "mem/protocol/CacheMsg.hh" 402665SN/A#include "mem/protocol/CacheRequestType.hh" 418715SN/A#include "mem/protocol/MachineType.hh" 428922SN/A#include "mem/ruby/common/Address.hh" 432497SN/A#include "mem/ruby/common/DataBlock.hh" 442497SN/A#include "mem/ruby/common/Global.hh" 452497SN/A#include "mem/ruby/profiler/CacheProfiler.hh" 462982SN/A#include "mem/ruby/recorder/CacheRecorder.hh" 4710405Sandreas.hansson@arm.com#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 482497SN/A#include "mem/ruby/slicc_interface/AbstractController.hh" 492497SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 502846SN/A#include "mem/ruby/system/LRUPolicy.hh" 512548SN/A#include "mem/ruby/system/PseudoLRUPolicy.hh" 5210405Sandreas.hansson@arm.com#include "mem/ruby/system/System.hh" 5310405Sandreas.hansson@arm.com#include "params/RubyCache.hh" 5410405Sandreas.hansson@arm.com#include "sim/sim_object.hh" 559524SN/A 562497SN/Aclass CacheMemory : public SimObject 5710405Sandreas.hansson@arm.com{ 5810719SMarco.Balboni@ARM.com public: 5910719SMarco.Balboni@ARM.com typedef RubyCacheParams Params; 607523SN/A CacheMemory(const Params *p); 618851SN/A ~CacheMemory(); 628948SN/A 638948SN/A void init(); 648851SN/A 659095SN/A // Public Methods 6610405Sandreas.hansson@arm.com void printConfig(std::ostream& out); 678922SN/A 689715SN/A // perform a cache access and see if we hit or not. Return true on a hit. 699715SN/A bool tryCacheAccess(const Address& address, CacheRequestType type, 7010713Sandreas.hansson@arm.com DataBlock*& data_ptr); 7110713Sandreas.hansson@arm.com 728851SN/A // similar to above, but doesn't require full access check 738851SN/A bool testCacheAccess(const Address& address, CacheRequestType type, 748948SN/A DataBlock*& data_ptr); 758948SN/A 768915SN/A // tests to see if an address is present in the cache 779031SN/A bool isTagPresent(const Address& address) const; 789095SN/A 7910405Sandreas.hansson@arm.com // Returns true if there is: 809036SN/A // a) a tag match on this address or there is 818922SN/A // b) an unused line in the same cache "way" 829715SN/A bool cacheAvail(const Address& address) const; 839715SN/A 8410713Sandreas.hansson@arm.com // find an unused entry and sets the tag appropriate for the address 8510713Sandreas.hansson@arm.com void allocate(const Address& address, AbstractCacheEntry* new_entry); 8610713Sandreas.hansson@arm.com 878915SN/A // Explicitly free up this address 888915SN/A void deallocate(const Address& address); 898948SN/A 908851SN/A // Returns with the physical address of the conflicting cache line 919095SN/A Address cacheProbe(const Address& address) const; 9210888Sandreas.hansson@arm.com 938922SN/A // looks an address up in the cache 949715SN/A AbstractCacheEntry& lookup(const Address& address); 959715SN/A const AbstractCacheEntry& lookup(const Address& address) const; 969716SN/A 978851SN/A // Get/Set permission of cache block 988851SN/A AccessPermission getPermission(const Address& address) const; 9910402SN/A void changePermission(const Address& address, AccessPermission new_perm); 10010402SN/A 10110402SN/A int getLatency() const { return m_latency; } 1027523SN/A 1037523SN/A // Hook for checkpointing the contents of the cache 1047523SN/A void recordCacheContents(CacheRecorder& tr) const; 10510405Sandreas.hansson@arm.com void 1069715SN/A setAsInstructionCache(bool is_icache) 10710405Sandreas.hansson@arm.com { 10810405Sandreas.hansson@arm.com m_is_instruction_only_cache = is_icache; 10910405Sandreas.hansson@arm.com } 11010405Sandreas.hansson@arm.com 11110405Sandreas.hansson@arm.com // Set this address to most recently used 11210405Sandreas.hansson@arm.com void setMRU(const Address& address); 11310405Sandreas.hansson@arm.com 11410405Sandreas.hansson@arm.com void profileMiss(const CacheMsg & msg); 1159715SN/A 1169715SN/A void getMemoryValue(const Address& addr, char* value, 1172568SN/A unsigned int size_in_bytes); 11810405Sandreas.hansson@arm.com void setMemoryValue(const Address& addr, char* value, 1192568SN/A unsigned int size_in_bytes); 1209278SN/A 12110405Sandreas.hansson@arm.com void setLocked (const Address& addr, int context); 1229278SN/A void clearLocked (const Address& addr); 1238948SN/A bool isLocked (const Address& addr, int context); 1248948SN/A // Print cache contents 12510405Sandreas.hansson@arm.com void print(std::ostream& out) const; 1269088SN/A void printData(std::ostream& out) const; 12710405Sandreas.hansson@arm.com 12810405Sandreas.hansson@arm.com void clearStats() const; 12910405Sandreas.hansson@arm.com void printStats(std::ostream& out) const; 13010405Sandreas.hansson@arm.com 1318711SN/A private: 1328711SN/A // convert a Address to its location in the cache 1332568SN/A Index addressToCacheSet(const Address& address) const; 1349036SN/A 13510405Sandreas.hansson@arm.com // Given a cache tag: returns the index of the tag in a set. 1363244SN/A // returns -1 if the tag is not found. 1373244SN/A int findTagInSet(Index line, const Address& tag) const; 1388948SN/A int findTagInSetIgnorePermissions(Index cacheSet, 13910405Sandreas.hansson@arm.com const Address& tag) const; 1403244SN/A 14110883Sali.jafri@arm.com // Private copy constructor and assignment operator 14210883Sali.jafri@arm.com CacheMemory(const CacheMemory& obj); 14310883Sali.jafri@arm.com CacheMemory& operator=(const CacheMemory& obj); 14410883Sali.jafri@arm.com 14510883Sali.jafri@arm.com private: 14610883Sali.jafri@arm.com const std::string m_cache_name; 1478975SN/A int m_latency; 1489032SN/A 1493244SN/A // Data Members (m_prefix) 1509091SN/A bool m_is_instruction_only_cache; 1519091SN/A bool m_is_data_only_cache; 15210656Sandreas.hansson@arm.com 15310656Sandreas.hansson@arm.com // The first index is the # of cache lines. 15410656Sandreas.hansson@arm.com // The second index is the the amount associativity. 15510656Sandreas.hansson@arm.com m5::hash_map<Address, int> m_tag_index; 1569091SN/A Vector<Vector<AbstractCacheEntry*> > m_cache; 1579612SN/A Vector<Vector<int> > m_locked; 1589712SN/A 1599612SN/A AbstractReplacementPolicy *m_replacementPolicy_ptr; 16010405Sandreas.hansson@arm.com 1619033SN/A CacheProfiler* m_profiler_ptr; 1629715SN/A 16310405Sandreas.hansson@arm.com int m_cache_size; 1648949SN/A std::string m_policy; 1653244SN/A int m_cache_num_sets; 1663244SN/A int m_cache_num_set_bits; 1673244SN/A int m_cache_assoc; 16810405Sandreas.hansson@arm.com}; 1699091SN/A 1709091SN/A#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 1715197SN/A 1729712SN/A