CacheMemory.hh revision 6876
112653Sandreas.sandberg@arm.com/* 212653Sandreas.sandberg@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 312653Sandreas.sandberg@arm.com * All rights reserved. 412653Sandreas.sandberg@arm.com * 512653Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 612653Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 712653Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 812653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 912653Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1012653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1112653Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1212653Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1312653Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1412653Sandreas.sandberg@arm.com * this software without specific prior written permission. 1512653Sandreas.sandberg@arm.com * 1612653Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712653Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812653Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912653Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012653Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112653Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212653Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312653Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412653Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512653Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612653Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712653Sandreas.sandberg@arm.com */ 2812653Sandreas.sandberg@arm.com 2912653Sandreas.sandberg@arm.com/* 3012653Sandreas.sandberg@arm.com * CacheMemory.hh 3112653Sandreas.sandberg@arm.com * 3212653Sandreas.sandberg@arm.com * Description: 3312653Sandreas.sandberg@arm.com * 3412653Sandreas.sandberg@arm.com * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $ 3512653Sandreas.sandberg@arm.com * 3612653Sandreas.sandberg@arm.com */ 3712653Sandreas.sandberg@arm.com 3812653Sandreas.sandberg@arm.com#ifndef CACHEMEMORY_H 3912653Sandreas.sandberg@arm.com#define CACHEMEMORY_H 4012653Sandreas.sandberg@arm.com 4112653Sandreas.sandberg@arm.com#include "sim/sim_object.hh" 4212653Sandreas.sandberg@arm.com#include "params/RubyCache.hh" 4312653Sandreas.sandberg@arm.com 4412653Sandreas.sandberg@arm.com#include "mem/ruby/common/Global.hh" 4512653Sandreas.sandberg@arm.com#include "mem/protocol/AccessPermission.hh" 4612653Sandreas.sandberg@arm.com#include "mem/ruby/common/Address.hh" 4712653Sandreas.sandberg@arm.com#include "mem/ruby/recorder/CacheRecorder.hh" 4812656Sandreas.sandberg@arm.com#include "mem/protocol/CacheRequestType.hh" 4912653Sandreas.sandberg@arm.com#include "mem/gems_common/Vector.hh" 5012653Sandreas.sandberg@arm.com#include "mem/ruby/common/DataBlock.hh" 5112653Sandreas.sandberg@arm.com#include "mem/protocol/MachineType.hh" 5212653Sandreas.sandberg@arm.com#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 5312653Sandreas.sandberg@arm.com#include "mem/ruby/system/PseudoLRUPolicy.hh" 5412653Sandreas.sandberg@arm.com#include "mem/ruby/system/LRUPolicy.hh" 5512653Sandreas.sandberg@arm.com#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 5612653Sandreas.sandberg@arm.com#include "mem/ruby/system/System.hh" 5712653Sandreas.sandberg@arm.com#include "mem/ruby/slicc_interface/AbstractController.hh" 5812653Sandreas.sandberg@arm.com#include "mem/ruby/profiler/CacheProfiler.hh" 5912653Sandreas.sandberg@arm.com#include "mem/protocol/CacheMsg.hh" 6012653Sandreas.sandberg@arm.com#include "base/hashmap.hh" 6112653Sandreas.sandberg@arm.com#include <vector> 6212653Sandreas.sandberg@arm.com 6312653Sandreas.sandberg@arm.comclass CacheMemory : public SimObject { 6412653Sandreas.sandberg@arm.compublic: 6512653Sandreas.sandberg@arm.com 6612653Sandreas.sandberg@arm.com typedef RubyCacheParams Params; 6712653Sandreas.sandberg@arm.com // Constructors 6812653Sandreas.sandberg@arm.com CacheMemory(const Params *p); 6912653Sandreas.sandberg@arm.com // CacheMemory(const string & name); 7012653Sandreas.sandberg@arm.com void init(); 7112653Sandreas.sandberg@arm.com 7212653Sandreas.sandberg@arm.com // Destructor 7312653Sandreas.sandberg@arm.com ~CacheMemory(); 7412653Sandreas.sandberg@arm.com 7512653Sandreas.sandberg@arm.com // factory 7612653Sandreas.sandberg@arm.com // static CacheMemory* createCache(int level, int num, char split_type, AbstractCacheEntry* (*entry_factory)()); 7712653Sandreas.sandberg@arm.com // static CacheMemory* getCache(int cache_id); 7812653Sandreas.sandberg@arm.com 7912653Sandreas.sandberg@arm.com // Public Methods 8012653Sandreas.sandberg@arm.com void printConfig(ostream& out); 8112653Sandreas.sandberg@arm.com 8212653Sandreas.sandberg@arm.com // perform a cache access and see if we hit or not. Return true on a hit. 8312653Sandreas.sandberg@arm.com bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); 8412653Sandreas.sandberg@arm.com 8512653Sandreas.sandberg@arm.com // similar to above, but doesn't require full access check 8612653Sandreas.sandberg@arm.com bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); 8712653Sandreas.sandberg@arm.com 8812653Sandreas.sandberg@arm.com // tests to see if an address is present in the cache 8912653Sandreas.sandberg@arm.com bool isTagPresent(const Address& address) const; 9012653Sandreas.sandberg@arm.com 9112653Sandreas.sandberg@arm.com // Returns true if there is: 9212653Sandreas.sandberg@arm.com // a) a tag match on this address or there is 9312653Sandreas.sandberg@arm.com // b) an unused line in the same cache "way" 9412653Sandreas.sandberg@arm.com bool cacheAvail(const Address& address) const; 9512653Sandreas.sandberg@arm.com 9612656Sandreas.sandberg@arm.com // find an unused entry and sets the tag appropriate for the address 9712656Sandreas.sandberg@arm.com void allocate(const Address& address, AbstractCacheEntry* new_entry); 9812656Sandreas.sandberg@arm.com 9912656Sandreas.sandberg@arm.com // Explicitly free up this address 10012656Sandreas.sandberg@arm.com void deallocate(const Address& address); 10112656Sandreas.sandberg@arm.com 10212656Sandreas.sandberg@arm.com // Returns with the physical address of the conflicting cache line 10312656Sandreas.sandberg@arm.com Address cacheProbe(const Address& address) const; 10412656Sandreas.sandberg@arm.com 10512656Sandreas.sandberg@arm.com // looks an address up in the cache 10612653Sandreas.sandberg@arm.com AbstractCacheEntry& lookup(const Address& address); 10712656Sandreas.sandberg@arm.com const AbstractCacheEntry& lookup(const Address& address) const; 10812653Sandreas.sandberg@arm.com 10912653Sandreas.sandberg@arm.com // Get/Set permission of cache block 11012653Sandreas.sandberg@arm.com AccessPermission getPermission(const Address& address) const; 11112653Sandreas.sandberg@arm.com void changePermission(const Address& address, AccessPermission new_perm); 11212653Sandreas.sandberg@arm.com 11312653Sandreas.sandberg@arm.com static int numberOfLastLevelCaches(); 11412653Sandreas.sandberg@arm.com 11512653Sandreas.sandberg@arm.com int getLatency() const { return m_latency; } 11612653Sandreas.sandberg@arm.com 11712653Sandreas.sandberg@arm.com // Hook for checkpointing the contents of the cache 11812653Sandreas.sandberg@arm.com void recordCacheContents(CacheRecorder& tr) const; 11912653Sandreas.sandberg@arm.com void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; } 12012653Sandreas.sandberg@arm.com 12112653Sandreas.sandberg@arm.com // Set this address to most recently used 12212653Sandreas.sandberg@arm.com void setMRU(const Address& address); 12312653Sandreas.sandberg@arm.com 12412653Sandreas.sandberg@arm.com void profileMiss(const CacheMsg & msg); 12512653Sandreas.sandberg@arm.com 12612653Sandreas.sandberg@arm.com void getMemoryValue(const Address& addr, char* value, 12712653Sandreas.sandberg@arm.com unsigned int size_in_bytes ); 12812653Sandreas.sandberg@arm.com void setMemoryValue(const Address& addr, char* value, 12912653Sandreas.sandberg@arm.com unsigned int size_in_bytes ); 13012653Sandreas.sandberg@arm.com 13112653Sandreas.sandberg@arm.com void setLocked (const Address& addr, int context); 13212653Sandreas.sandberg@arm.com void clearLocked (const Address& addr); 13312653Sandreas.sandberg@arm.com bool isLocked (const Address& addr, int context); 13412653Sandreas.sandberg@arm.com // Print cache contents 13512653Sandreas.sandberg@arm.com void print(ostream& out) const; 13612653Sandreas.sandberg@arm.com void printData(ostream& out) const; 13712653Sandreas.sandberg@arm.com 13812653Sandreas.sandberg@arm.com void clearStats() const; 13912653Sandreas.sandberg@arm.com void printStats(ostream& out) const; 14012653Sandreas.sandberg@arm.com 14112653Sandreas.sandberg@arm.comprivate: 14212656Sandreas.sandberg@arm.com // Private Methods 14312656Sandreas.sandberg@arm.com 14412656Sandreas.sandberg@arm.com // convert a Address to its location in the cache 14512653Sandreas.sandberg@arm.com Index addressToCacheSet(const Address& address) const; 14612653Sandreas.sandberg@arm.com 14712653Sandreas.sandberg@arm.com // Given a cache tag: returns the index of the tag in a set. 14812653Sandreas.sandberg@arm.com // returns -1 if the tag is not found. 149 int findTagInSet(Index line, const Address& tag) const; 150 int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const; 151 152 // Private copy constructor and assignment operator 153 CacheMemory(const CacheMemory& obj); 154 CacheMemory& operator=(const CacheMemory& obj); 155 156private: 157 const string m_cache_name; 158 AbstractController* m_controller; 159 int m_latency; 160 161 // Data Members (m_prefix) 162 bool m_is_instruction_only_cache; 163 bool m_is_data_only_cache; 164 165 // The first index is the # of cache lines. 166 // The second index is the the amount associativity. 167 m5::hash_map<Address, int> m_tag_index; 168 Vector<Vector<AbstractCacheEntry*> > m_cache; 169 Vector<Vector<int> > m_locked; 170 171 AbstractReplacementPolicy *m_replacementPolicy_ptr; 172 173 CacheProfiler* m_profiler_ptr; 174 175 int m_cache_num_sets; 176 int m_cache_num_set_bits; 177 int m_cache_assoc; 178 179 static Vector< CacheMemory* > m_all_caches; 180 181 static int m_num_last_level_caches; 182 static MachineType m_last_level_machine_type; 183 184}; 185 186#endif //CACHEMEMORY_H 187 188