CacheMemory.hh revision 10980
16145SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310973Sdavid.hashe@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 46145SN/A * All rights reserved. 56145SN/A * 66145SN/A * Redistribution and use in source and binary forms, with or without 76145SN/A * modification, are permitted provided that the following conditions are 86145SN/A * met: redistributions of source code must retain the above copyright 96145SN/A * notice, this list of conditions and the following disclaimer; 106145SN/A * redistributions in binary form must reproduce the above copyright 116145SN/A * notice, this list of conditions and the following disclaimer in the 126145SN/A * documentation and/or other materials provided with the distribution; 136145SN/A * neither the name of the copyright holders nor the names of its 146145SN/A * contributors may be used to endorse or promote products derived from 156145SN/A * this software without specific prior written permission. 166145SN/A * 176145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286145SN/A */ 296145SN/A 3010441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3110441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 326145SN/A 337055SN/A#include <string> 346145SN/A#include <vector> 356145SN/A 367039SN/A#include "base/hashmap.hh" 379104SN/A#include "base/statistics.hh" 3810301Snilay@cs.wisc.edu#include "mem/protocol/CacheRequestType.hh" 399105SN/A#include "mem/protocol/CacheResourceType.hh" 408174SN/A#include "mem/protocol/RubyRequest.hh" 417039SN/A#include "mem/ruby/common/DataBlock.hh" 427039SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 437039SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4410970Sdavid.hashe@amd.com#include "mem/ruby/structures/AbstractReplacementPolicy.hh" 4510301Snilay@cs.wisc.edu#include "mem/ruby/structures/BankedArray.hh" 4610301Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 477039SN/A#include "params/RubyCache.hh" 487039SN/A#include "sim/sim_object.hh" 496145SN/A 507039SN/Aclass CacheMemory : public SimObject 517039SN/A{ 527039SN/A public: 536876SN/A typedef RubyCacheParams Params; 547039SN/A CacheMemory(const Params *p); 557039SN/A ~CacheMemory(); 566145SN/A 577039SN/A void init(); 586145SN/A 597039SN/A // Public Methods 607039SN/A // perform a cache access and see if we hit or not. Return true on a hit. 618165SN/A bool tryCacheAccess(const Address& address, RubyRequestType type, 627039SN/A DataBlock*& data_ptr); 636145SN/A 647039SN/A // similar to above, but doesn't require full access check 658165SN/A bool testCacheAccess(const Address& address, RubyRequestType type, 667039SN/A DataBlock*& data_ptr); 676145SN/A 687039SN/A // tests to see if an address is present in the cache 697039SN/A bool isTagPresent(const Address& address) const; 706145SN/A 717039SN/A // Returns true if there is: 727039SN/A // a) a tag match on this address or there is 737039SN/A // b) an unused line in the same cache "way" 747039SN/A bool cacheAvail(const Address& address) const; 756145SN/A 767039SN/A // find an unused entry and sets the tag appropriate for the address 7710974Sdavid.hashe@amd.com AbstractCacheEntry* allocate(const Address& address, 7810974Sdavid.hashe@amd.com AbstractCacheEntry* new_entry, bool touch); 7910974Sdavid.hashe@amd.com AbstractCacheEntry* allocate(const Address& address, 8010974Sdavid.hashe@amd.com AbstractCacheEntry* new_entry) 8110974Sdavid.hashe@amd.com { 8210974Sdavid.hashe@amd.com return allocate(address, new_entry, true); 8310974Sdavid.hashe@amd.com } 848193SN/A void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 858193SN/A { 8610974Sdavid.hashe@amd.com allocate(address, new_entry, true); 878193SN/A } 886145SN/A 897039SN/A // Explicitly free up this address 907039SN/A void deallocate(const Address& address); 916145SN/A 927039SN/A // Returns with the physical address of the conflicting cache line 937039SN/A Address cacheProbe(const Address& address) const; 946145SN/A 957039SN/A // looks an address up in the cache 967839SN/A AbstractCacheEntry* lookup(const Address& address); 977839SN/A const AbstractCacheEntry* lookup(const Address& address) const; 986145SN/A 999499SN/A Cycles getLatency() const { return m_latency; } 10010969Sdavid.hashe@amd.com Cycles getTagLatency() const { return tagArray.getLatency(); } 10110969Sdavid.hashe@amd.com Cycles getDataLatency() const { return dataArray.getLatency(); } 10210969Sdavid.hashe@amd.com 10310980Sdavid.hashe@amd.com bool isBlockInvalid(int64 cache_set, int64 loc); 10410980Sdavid.hashe@amd.com bool isBlockNotBusy(int64 cache_set, int64 loc); 1056285SN/A 1067039SN/A // Hook for checkpointing the contents of the cache 1078683SN/A void recordCacheContents(int cntrl, CacheRecorder* tr) const; 1086145SN/A 1097039SN/A // Set this address to most recently used 1107039SN/A void setMRU(const Address& address); 1116145SN/A 1127039SN/A void setLocked (const Address& addr, int context); 1137039SN/A void clearLocked (const Address& addr); 1147039SN/A bool isLocked (const Address& addr, int context); 1159692SN/A 1167039SN/A // Print cache contents 1177055SN/A void print(std::ostream& out) const; 1187055SN/A void printData(std::ostream& out) const; 1196145SN/A 1209692SN/A void regStats(); 1219692SN/A bool checkResourceAvailable(CacheResourceType res, Address addr); 12210978Sdavid.hashe@amd.com void recordRequestType(CacheRequestType requestType, Address addr); 1236374SN/A 1249692SN/A public: 1259692SN/A Stats::Scalar m_demand_hits; 1269692SN/A Stats::Scalar m_demand_misses; 1279692SN/A Stats::Formula m_demand_accesses; 1289692SN/A 1299692SN/A Stats::Scalar m_sw_prefetches; 1309692SN/A Stats::Scalar m_hw_prefetches; 1319692SN/A Stats::Formula m_prefetches; 1329692SN/A 1339692SN/A Stats::Vector m_accessModeType; 1349104SN/A 1359104SN/A Stats::Scalar numDataArrayReads; 1369104SN/A Stats::Scalar numDataArrayWrites; 1379104SN/A Stats::Scalar numTagArrayReads; 1389104SN/A Stats::Scalar numTagArrayWrites; 1399104SN/A 1409105SN/A Stats::Scalar numTagArrayStalls; 1419105SN/A Stats::Scalar numDataArrayStalls; 1429692SN/A 14310973Sdavid.hashe@amd.com int getCacheSize() const { return m_cache_size; } 14410973Sdavid.hashe@amd.com int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } 14510973Sdavid.hashe@amd.com Address getAddressAtIdx(int idx) const; 14610973Sdavid.hashe@amd.com 1477039SN/A private: 1487039SN/A // convert a Address to its location in the cache 14910314Snilay@cs.wisc.edu int64 addressToCacheSet(const Address& address) const; 1506145SN/A 1517039SN/A // Given a cache tag: returns the index of the tag in a set. 1527039SN/A // returns -1 if the tag is not found. 15310314Snilay@cs.wisc.edu int findTagInSet(int64 line, const Address& tag) const; 15410314Snilay@cs.wisc.edu int findTagInSetIgnorePermissions(int64 cacheSet, 1557039SN/A const Address& tag) const; 1566145SN/A 1577039SN/A // Private copy constructor and assignment operator 1587039SN/A CacheMemory(const CacheMemory& obj); 1597039SN/A CacheMemory& operator=(const CacheMemory& obj); 1606145SN/A 1617039SN/A private: 1629499SN/A Cycles m_latency; 1636145SN/A 1647039SN/A // Data Members (m_prefix) 1657039SN/A bool m_is_instruction_only_cache; 1666285SN/A 1677039SN/A // The first index is the # of cache lines. 1687039SN/A // The second index is the the amount associativity. 1697039SN/A m5::hash_map<Address, int> m_tag_index; 1707454SN/A std::vector<std::vector<AbstractCacheEntry*> > m_cache; 1716145SN/A 1727039SN/A AbstractReplacementPolicy *m_replacementPolicy_ptr; 1736145SN/A 1749105SN/A BankedArray dataArray; 1759105SN/A BankedArray tagArray; 1769105SN/A 1777039SN/A int m_cache_size; 1787039SN/A int m_cache_num_sets; 1797039SN/A int m_cache_num_set_bits; 1807039SN/A int m_cache_assoc; 1817564SN/A int m_start_index_bit; 1829105SN/A bool m_resource_stalls; 1836145SN/A}; 1846145SN/A 1859554SN/Astd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 1869554SN/A 18710441Snilay@cs.wisc.edu#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 188