CacheMemory.hh revision 10969
12135SN/A/* 22135SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu */ 285268Sksewell@umich.edu 295268Sksewell@umich.edu#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 302706Sksewell@umich.edu#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 312038SN/A 322038SN/A#include <string> 332038SN/A#include <vector> 342038SN/A 352038SN/A#include "base/hashmap.hh" 362038SN/A#include "base/statistics.hh" 372038SN/A#include "mem/protocol/CacheRequestType.hh" 382135SN/A#include "mem/protocol/CacheResourceType.hh" 392038SN/A#include "mem/protocol/RubyRequest.hh" 402038SN/A#include "mem/ruby/common/DataBlock.hh" 412038SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 422038SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 432038SN/A#include "mem/ruby/structures/BankedArray.hh" 442038SN/A#include "mem/ruby/structures/LRUPolicy.hh" 452038SN/A#include "mem/ruby/structures/PseudoLRUPolicy.hh" 462038SN/A#include "mem/ruby/system/CacheRecorder.hh" 472038SN/A#include "params/RubyCache.hh" 482038SN/A#include "sim/sim_object.hh" 492686Sksewell@umich.edu 502686Sksewell@umich.educlass CacheMemory : public SimObject 512686Sksewell@umich.edu{ 522686Sksewell@umich.edu public: 532686Sksewell@umich.edu typedef RubyCacheParams Params; 542686Sksewell@umich.edu CacheMemory(const Params *p); 552686Sksewell@umich.edu ~CacheMemory(); 562686Sksewell@umich.edu 572686Sksewell@umich.edu void init(); 582686Sksewell@umich.edu 592686Sksewell@umich.edu // Public Methods 602686Sksewell@umich.edu // perform a cache access and see if we hit or not. Return true on a hit. 612686Sksewell@umich.edu bool tryCacheAccess(const Address& address, RubyRequestType type, 622686Sksewell@umich.edu DataBlock*& data_ptr); 632038SN/A 642038SN/A // similar to above, but doesn't require full access check 652038SN/A bool testCacheAccess(const Address& address, RubyRequestType type, 662038SN/A DataBlock*& data_ptr); 672686Sksewell@umich.edu 682038SN/A // tests to see if an address is present in the cache 692686Sksewell@umich.edu bool isTagPresent(const Address& address) const; 702686Sksewell@umich.edu 712686Sksewell@umich.edu // Returns true if there is: 722686Sksewell@umich.edu // a) a tag match on this address or there is 732686Sksewell@umich.edu // b) an unused line in the same cache "way" 742686Sksewell@umich.edu bool cacheAvail(const Address& address) const; 752686Sksewell@umich.edu 762686Sksewell@umich.edu // find an unused entry and sets the tag appropriate for the address 772686Sksewell@umich.edu AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry); 782686Sksewell@umich.edu void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 792686Sksewell@umich.edu { 802686Sksewell@umich.edu allocate(address, new_entry); 812686Sksewell@umich.edu } 822686Sksewell@umich.edu 832686Sksewell@umich.edu // Explicitly free up this address 842686Sksewell@umich.edu void deallocate(const Address& address); 852686Sksewell@umich.edu 862038SN/A // Returns with the physical address of the conflicting cache line 872038SN/A Address cacheProbe(const Address& address) const; 882038SN/A 892686Sksewell@umich.edu // looks an address up in the cache 904661Sksewell@umich.edu AbstractCacheEntry* lookup(const Address& address); 914661Sksewell@umich.edu const AbstractCacheEntry* lookup(const Address& address) const; 924661Sksewell@umich.edu 934661Sksewell@umich.edu Cycles getLatency() const { return m_latency; } 945222Sksewell@umich.edu Cycles getTagLatency() const { return tagArray.getLatency(); } 955222Sksewell@umich.edu Cycles getDataLatency() const { return dataArray.getLatency(); } 965222Sksewell@umich.edu 975222Sksewell@umich.edu 984661Sksewell@umich.edu // Hook for checkpointing the contents of the cache 992038SN/A void recordCacheContents(int cntrl, CacheRecorder* tr) const; 1002686Sksewell@umich.edu 1012686Sksewell@umich.edu // Set this address to most recently used 1022686Sksewell@umich.edu void setMRU(const Address& address); 1032686Sksewell@umich.edu 1042686Sksewell@umich.edu void setLocked (const Address& addr, int context); 1052686Sksewell@umich.edu void clearLocked (const Address& addr); 1062686Sksewell@umich.edu bool isLocked (const Address& addr, int context); 1076314Sgblack@eecs.umich.edu 1082686Sksewell@umich.edu // Print cache contents 1092686Sksewell@umich.edu void print(std::ostream& out) const; 1106314Sgblack@eecs.umich.edu void printData(std::ostream& out) const; 1112686Sksewell@umich.edu 1126314Sgblack@eecs.umich.edu void regStats(); 1136314Sgblack@eecs.umich.edu bool checkResourceAvailable(CacheResourceType res, Address addr); 1146314Sgblack@eecs.umich.edu void recordRequestType(CacheRequestType requestType); 1152686Sksewell@umich.edu 1162686Sksewell@umich.edu public: 1172686Sksewell@umich.edu Stats::Scalar m_demand_hits; 1182686Sksewell@umich.edu Stats::Scalar m_demand_misses; 1192686Sksewell@umich.edu Stats::Formula m_demand_accesses; 1202686Sksewell@umich.edu 1212686Sksewell@umich.edu Stats::Scalar m_sw_prefetches; 1222686Sksewell@umich.edu Stats::Scalar m_hw_prefetches; 1232686Sksewell@umich.edu Stats::Formula m_prefetches; 1242687Sksewell@umich.edu 1252686Sksewell@umich.edu Stats::Vector m_accessModeType; 1262686Sksewell@umich.edu 1272686Sksewell@umich.edu Stats::Scalar numDataArrayReads; 1282686Sksewell@umich.edu Stats::Scalar numDataArrayWrites; 1296314Sgblack@eecs.umich.edu Stats::Scalar numTagArrayReads; 1302686Sksewell@umich.edu Stats::Scalar numTagArrayWrites; 1316314Sgblack@eecs.umich.edu 1326314Sgblack@eecs.umich.edu Stats::Scalar numTagArrayStalls; 1332686Sksewell@umich.edu Stats::Scalar numDataArrayStalls; 1342686Sksewell@umich.edu 1356314Sgblack@eecs.umich.edu private: 1362686Sksewell@umich.edu // convert a Address to its location in the cache 1372686Sksewell@umich.edu int64 addressToCacheSet(const Address& address) const; 1386383Sgblack@eecs.umich.edu 1396383Sgblack@eecs.umich.edu // Given a cache tag: returns the index of the tag in a set. 1402686Sksewell@umich.edu // returns -1 if the tag is not found. 1414675Sksewell@umich.edu int findTagInSet(int64 line, const Address& tag) const; 1424675Sksewell@umich.edu int findTagInSetIgnorePermissions(int64 cacheSet, 1432686Sksewell@umich.edu const Address& tag) const; 1446383Sgblack@eecs.umich.edu 1452686Sksewell@umich.edu // Private copy constructor and assignment operator 1462686Sksewell@umich.edu CacheMemory(const CacheMemory& obj); 1472686Sksewell@umich.edu CacheMemory& operator=(const CacheMemory& obj); 1482686Sksewell@umich.edu 1492686Sksewell@umich.edu private: 1502686Sksewell@umich.edu Cycles m_latency; 1512686Sksewell@umich.edu 1522686Sksewell@umich.edu // Data Members (m_prefix) 1532686Sksewell@umich.edu bool m_is_instruction_only_cache; 1542687Sksewell@umich.edu 1552686Sksewell@umich.edu // The first index is the # of cache lines. 1562686Sksewell@umich.edu // The second index is the the amount associativity. 1576383Sgblack@eecs.umich.edu m5::hash_map<Address, int> m_tag_index; 1582686Sksewell@umich.edu std::vector<std::vector<AbstractCacheEntry*> > m_cache; 1594661Sksewell@umich.edu 1602686Sksewell@umich.edu AbstractReplacementPolicy *m_replacementPolicy_ptr; 1612686Sksewell@umich.edu 1622686Sksewell@umich.edu BankedArray dataArray; 1636383Sgblack@eecs.umich.edu BankedArray tagArray; 1642686Sksewell@umich.edu 1652686Sksewell@umich.edu int m_cache_size; 1662686Sksewell@umich.edu std::string m_policy; 1672686Sksewell@umich.edu int m_cache_num_sets; 1682686Sksewell@umich.edu int m_cache_num_set_bits; 1692686Sksewell@umich.edu int m_cache_assoc; 1702686Sksewell@umich.edu int m_start_index_bit; 1712686Sksewell@umich.edu bool m_resource_stalls; 1722686Sksewell@umich.edu}; 1732686Sksewell@umich.edu 1745222Sksewell@umich.edustd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 1752686Sksewell@umich.edu 1762686Sksewell@umich.edu#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 1778738Sgblack@eecs.umich.edu