BankedArray.cc revision 11793:ef606668d247
12391SN/A/* 210482Sandreas.hansson@arm.com * Copyright (c) 2012 Advanced Micro Devices, Inc. 37733SAli.Saidi@ARM.com * All rights reserved. 47733SAli.Saidi@ARM.com * 57733SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67733SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77733SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87733SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97733SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107733SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117733SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127733SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137733SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142391SN/A * this software without specific prior written permission. 152391SN/A * 162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272391SN/A * 282391SN/A * Author: Brad Beckmann 292391SN/A * 302391SN/A */ 312391SN/A 322391SN/A#include "mem/ruby/structures/BankedArray.hh" 332391SN/A 342391SN/A#include "base/intmath.hh" 352391SN/A#include "mem/ruby/system/RubySystem.hh" 362665Ssaidi@eecs.umich.edu 378931Sandreas.hansson@arm.comBankedArray::BankedArray(unsigned int banks, Cycles accessLatency, 382391SN/A unsigned int startIndexBit, RubySystem *rs) 392391SN/A : m_ruby_system(rs) 409293Sandreas.hansson@arm.com{ 419293Sandreas.hansson@arm.com this->banks = banks; 429293Sandreas.hansson@arm.com this->accessLatency = accessLatency; 439293Sandreas.hansson@arm.com this->startIndexBit = startIndexBit; 449293Sandreas.hansson@arm.com 459293Sandreas.hansson@arm.com if (banks != 0) { 469293Sandreas.hansson@arm.com bankBits = floorLog2(banks); 479293Sandreas.hansson@arm.com } 489293Sandreas.hansson@arm.com 499293Sandreas.hansson@arm.com busyBanks.resize(banks); 509293Sandreas.hansson@arm.com} 519293Sandreas.hansson@arm.com 529293Sandreas.hansson@arm.combool 539356Snilay@cs.wisc.eduBankedArray::tryAccess(int64_t idx) 5410405Sandreas.hansson@arm.com{ 559293Sandreas.hansson@arm.com if (accessLatency == 0) 569293Sandreas.hansson@arm.com return true; 572394SN/A 582394SN/A unsigned int bank = mapIndexToBank(idx); 5910700Sandreas.hansson@arm.com assert(bank < banks); 6010700Sandreas.hansson@arm.com 6110700Sandreas.hansson@arm.com if (busyBanks[bank].endAccess >= curTick()) { 6210700Sandreas.hansson@arm.com return false; 6310700Sandreas.hansson@arm.com } 6410700Sandreas.hansson@arm.com 6510700Sandreas.hansson@arm.com return true; 6610700Sandreas.hansson@arm.com} 6710700Sandreas.hansson@arm.com 6810700Sandreas.hansson@arm.comvoid 6910700Sandreas.hansson@arm.comBankedArray::reserve(int64_t idx) 7010700Sandreas.hansson@arm.com{ 712391SN/A if (accessLatency == 0) 722391SN/A return; 739293Sandreas.hansson@arm.com 7410700Sandreas.hansson@arm.com unsigned int bank = mapIndexToBank(idx); 7510700Sandreas.hansson@arm.com assert(bank < banks); 7610700Sandreas.hansson@arm.com 7710700Sandreas.hansson@arm.com if (busyBanks[bank].endAccess >= curTick()) { 782391SN/A if (busyBanks[bank].startAccess == curTick() && 7910700Sandreas.hansson@arm.com busyBanks[bank].idx == idx) { 8010700Sandreas.hansson@arm.com // this is the same reservation (can happen when 8110700Sandreas.hansson@arm.com // e.g., reserve the same resource for read and write) 829293Sandreas.hansson@arm.com return; // OK 839293Sandreas.hansson@arm.com } else { 8410482Sandreas.hansson@arm.com panic("BankedArray reservation error"); 858931Sandreas.hansson@arm.com } 8610482Sandreas.hansson@arm.com } 8710482Sandreas.hansson@arm.com 882391SN/A busyBanks[bank].idx = idx; 898931Sandreas.hansson@arm.com busyBanks[bank].startAccess = curTick(); 9010482Sandreas.hansson@arm.com busyBanks[bank].endAccess = curTick() + 918931Sandreas.hansson@arm.com (accessLatency-1) * m_ruby_system->clockPeriod(); 928931Sandreas.hansson@arm.com} 938931Sandreas.hansson@arm.com 9410482Sandreas.hansson@arm.comunsigned int 9510482Sandreas.hansson@arm.comBankedArray::mapIndexToBank(int64_t idx) 9610482Sandreas.hansson@arm.com{ 979293Sandreas.hansson@arm.com if (banks == 1) { 989293Sandreas.hansson@arm.com return 0; 999293Sandreas.hansson@arm.com } 1009293Sandreas.hansson@arm.com return idx % banks; 10110482Sandreas.hansson@arm.com} 10210482Sandreas.hansson@arm.com