BankedArray.cc revision 10919:80069a602c83
1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Author: Brad Beckmann 29 * 30 */ 31 32#include "base/intmath.hh" 33#include "mem/ruby/structures/BankedArray.hh" 34#include "mem/ruby/system/System.hh" 35 36BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, 37 unsigned int startIndexBit, RubySystem *rs) 38 : m_ruby_system(rs) 39{ 40 this->banks = banks; 41 this->accessLatency = accessLatency; 42 this->startIndexBit = startIndexBit; 43 44 if (banks != 0) { 45 bankBits = floorLog2(banks); 46 } 47 48 busyBanks.resize(banks); 49} 50 51bool 52BankedArray::tryAccess(int64 idx) 53{ 54 if (accessLatency == 0) 55 return true; 56 57 unsigned int bank = mapIndexToBank(idx); 58 assert(bank < banks); 59 60 if (busyBanks[bank].endAccess >= curTick()) { 61 if (!(busyBanks[bank].startAccess == curTick() && 62 busyBanks[bank].idx == idx)) { 63 return false; 64 } else { 65 // We tried to allocate resources twice 66 // in the same cycle for the same addr 67 return true; 68 } 69 } 70 71 busyBanks[bank].idx = idx; 72 busyBanks[bank].startAccess = curTick(); 73 busyBanks[bank].endAccess = curTick() + 74 (accessLatency-1) * m_ruby_system->clockPeriod(); 75 76 return true; 77} 78 79unsigned int 80BankedArray::mapIndexToBank(int64 idx) 81{ 82 if (banks == 1) { 83 return 0; 84 } 85 return idx % banks; 86} 87