BankedArray.cc revision 9297 
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author: Brad Beckmann
29 *
30 */
31
32#include "base/intmath.hh"
33#include "mem/ruby/system/BankedArray.hh"
34#include "mem/ruby/system/System.hh"
35
36BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
37                         unsigned int startIndexBit)
38{
39    this->banks = banks;
40    this->accessLatency = accessLatency;
41    this->startIndexBit = startIndexBit;
42
43    if (banks != 0) {
44        bankBits = floorLog2(banks);
45    }
46
47    busyBanks.resize(banks);
48}
49
50bool
51BankedArray::tryAccess(Index idx)
52{
53    if (accessLatency == 0)
54        return true;
55
56    unsigned int bank = mapIndexToBank(idx);
57    assert(bank < banks);
58
59    if (busyBanks[bank].endAccess >= curTick()) {
60        if (!(busyBanks[bank].startAccess == curTick() &&
61            busyBanks[bank].idx == idx)) {
62            return false;
63        } else {
64            // We tried to allocate resources twice
65            // in the same cycle for the same addr
66            return true;
67        }
68    }
69
70    busyBanks[bank].idx = idx;
71    busyBanks[bank].startAccess = curTick();
72    busyBanks[bank].endAccess = curTick() +
73        (accessLatency-1) * g_system_ptr->clockPeriod();
74
75    return true;
76}
77
78unsigned int
79BankedArray::mapIndexToBank(Index idx)
80{
81    if (banks == 1) {
82        return 0;
83    }
84    return idx % banks;
85}
86