BankedArray.cc revision 9155 
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author: Brad Beckmann
29 *
30 */
31
32#include <vector>
33
34#include "base/intmath.hh"
35#include "mem/ruby/common/TypeDefines.hh"
36#include "mem/ruby/system/BankedArray.hh"
37#include "sim/eventq.hh"
38
39BankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) :
40    EventManager(&mainEventQueue)
41{
42    this->banks = banks;
43    this->accessLatency = accessLatency;
44    this->startIndexBit = startIndexBit;
45
46    if (banks != 0) {
47        bankBits = floorLog2(banks);
48    }
49
50    busyBanks.resize(banks);
51}
52
53bool
54BankedArray::tryAccess(Index idx)
55{
56    if (accessLatency == 0)
57        return true;
58
59    unsigned int bank = mapIndexToBank(idx);
60    assert(bank < banks);
61
62    if (busyBanks[bank].scheduled()) {
63        if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx == idx)) {
64            return false;
65        } else {
66            return true;  // We tried to allocate resources twice in the same cycle for the same addr
67        }
68    }
69
70    busyBanks[bank].idx = idx;
71    busyBanks[bank].startAccess = curTick();
72
73    // substract 1 so that next cycle the resource available
74    schedule(busyBanks[bank], curTick()+accessLatency-1);
75
76    return true;
77}
78
79unsigned int
80BankedArray::mapIndexToBank(Index idx)
81{
82    if (banks == 1) {
83        return 0;
84    }
85    return idx % banks;
86}
87