BankedArray.cc revision 10978
19155SN/A/* 29155SN/A * Copyright (c) 2012 Advanced Micro Devices, Inc. 39155SN/A * All rights reserved. 49155SN/A * 59155SN/A * Redistribution and use in source and binary forms, with or without 69155SN/A * modification, are permitted provided that the following conditions are 79155SN/A * met: redistributions of source code must retain the above copyright 89155SN/A * notice, this list of conditions and the following disclaimer; 99155SN/A * redistributions in binary form must reproduce the above copyright 109155SN/A * notice, this list of conditions and the following disclaimer in the 119155SN/A * documentation and/or other materials provided with the distribution; 129155SN/A * neither the name of the copyright holders nor the names of its 139155SN/A * contributors may be used to endorse or promote products derived from 149155SN/A * this software without specific prior written permission. 159155SN/A * 169155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279155SN/A * 289155SN/A * Author: Brad Beckmann 299155SN/A * 309155SN/A */ 319105SN/A 329297SN/A#include "base/intmath.hh" 3310301Snilay@cs.wisc.edu#include "mem/ruby/structures/BankedArray.hh" 349297SN/A#include "mem/ruby/system/System.hh" 359105SN/A 369297SN/ABankedArray::BankedArray(unsigned int banks, Cycles accessLatency, 3710919Sbrandon.potter@amd.com unsigned int startIndexBit, RubySystem *rs) 3810919Sbrandon.potter@amd.com : m_ruby_system(rs) 399105SN/A{ 409105SN/A this->banks = banks; 419105SN/A this->accessLatency = accessLatency; 429105SN/A this->startIndexBit = startIndexBit; 439105SN/A 449105SN/A if (banks != 0) { 459105SN/A bankBits = floorLog2(banks); 469105SN/A } 479105SN/A 489105SN/A busyBanks.resize(banks); 499105SN/A} 509105SN/A 519105SN/Abool 5210314Snilay@cs.wisc.eduBankedArray::tryAccess(int64 idx) 539105SN/A{ 549105SN/A if (accessLatency == 0) 559105SN/A return true; 569105SN/A 579105SN/A unsigned int bank = mapIndexToBank(idx); 589105SN/A assert(bank < banks); 599105SN/A 609297SN/A if (busyBanks[bank].endAccess >= curTick()) { 619105SN/A return false; 6210978Sdavid.hashe@amd.com } 6310978Sdavid.hashe@amd.com 6410978Sdavid.hashe@amd.com return true; 6510978Sdavid.hashe@amd.com} 6610978Sdavid.hashe@amd.com 6710978Sdavid.hashe@amd.comvoid 6810978Sdavid.hashe@amd.comBankedArray::reserve(int64 idx) 6910978Sdavid.hashe@amd.com{ 7010978Sdavid.hashe@amd.com if (accessLatency == 0) 7110978Sdavid.hashe@amd.com return; 7210978Sdavid.hashe@amd.com 7310978Sdavid.hashe@amd.com unsigned int bank = mapIndexToBank(idx); 7410978Sdavid.hashe@amd.com assert(bank < banks); 7510978Sdavid.hashe@amd.com 7610978Sdavid.hashe@amd.com if(busyBanks[bank].endAccess >= curTick()) { 7710978Sdavid.hashe@amd.com if (busyBanks[bank].startAccess == curTick() && 7810978Sdavid.hashe@amd.com busyBanks[bank].idx == idx) { 7910978Sdavid.hashe@amd.com // this is the same reservation (can happen when 8010978Sdavid.hashe@amd.com // e.g., reserve the same resource for read and write) 8110978Sdavid.hashe@amd.com return; // OK 829105SN/A } else { 8310978Sdavid.hashe@amd.com panic("BankedArray reservation error"); 849105SN/A } 859105SN/A } 869105SN/A 879105SN/A busyBanks[bank].idx = idx; 889105SN/A busyBanks[bank].startAccess = curTick(); 899297SN/A busyBanks[bank].endAccess = curTick() + 9010919Sbrandon.potter@amd.com (accessLatency-1) * m_ruby_system->clockPeriod(); 919105SN/A} 929105SN/A 939105SN/Aunsigned int 9410314Snilay@cs.wisc.eduBankedArray::mapIndexToBank(int64 idx) 959105SN/A{ 969105SN/A if (banks == 1) { 979105SN/A return 0; 989105SN/A } 999105SN/A return idx % banks; 1009105SN/A} 101