1/*
2 * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Authors: Lisa Hsu
34 */
35
36machine(MachineType:CorePair, "CP-like Core Coherence")
37 : Sequencer * sequencer;
38   Sequencer * sequencer1;
39   CacheMemory * L1Icache;
40   CacheMemory * L1D0cache;
41   CacheMemory * L1D1cache;
42   CacheMemory * L2cache;
43   int regionBufferNum;
44   bool send_evictions := "False";
45   Cycles issue_latency := 5;
46   Cycles l2_hit_latency := 18;
47
48  // BEGIN Core Buffers
49
50  // To the Network
51  MessageBuffer * requestFromCore, network="To", virtual_network="0", ordered="true", vnet_type="request";
52  MessageBuffer * responseFromCore, network="To", virtual_network="2", ordered="false", vnet_type="response";
53  MessageBuffer * unblockFromCore, network="To", virtual_network="4", ordered="false", vnet_type="unblock";
54
55  // From the Network
56  MessageBuffer * probeToCore, network="From", virtual_network="0", ordered="false", vnet_type="request";
57  MessageBuffer * responseToCore, network="From", virtual_network="2", ordered="false", vnet_type="response";
58
59  MessageBuffer * mandatoryQueue, ordered="false";
60  MessageBuffer * triggerQueue, ordered="true";
61
62  // END Core Buffers
63
64{
65  // BEGIN STATES
66  state_declaration(State, desc="Cache states", default="CorePair_State_I") {
67
68    I, AccessPermission:Invalid, desc="Invalid";
69    S, AccessPermission:Read_Only, desc="Shared";
70    E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership";
71    E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership";
72    Es, AccessPermission:Read_Write, desc="Exclusive in core";
73    O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line";
74    Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line";
75    M0, AccessPermission:Read_Write, desc="Modified with cluster ownership";
76    M1, AccessPermission:Read_Write, desc="Modified with cluster ownership";
77
78    // Transient States
79    I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
80    I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
81    I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well";
82    I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well";
83    I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well";
84    I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well";
85    I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
86    I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
87    I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters";
88
89    IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive";
90    IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive";
91    IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills";
92    IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
93    IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
94    F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received";
95    F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received";
96
97    ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack";
98    MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack";
99    MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
100    MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
101    S_F0, AccessPermission:Read_Only,  desc="Shared, filling L1";
102    S_F1, AccessPermission:Read_Only,  desc="Shared, filling L1";
103    S_F, AccessPermission:Read_Only,   desc="Shared, filling L1";
104    O_F0, AccessPermission:Read_Only,  desc="Owned, filling L1";
105    O_F1, AccessPermission:Read_Only,  desc="Owned, filling L1";
106    O_F,  AccessPermission:Read_Only,  desc="Owned, filling L1";
107    Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache";
108    Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache";
109    S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
110    S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
111    O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
112    O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
113    S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response";
114    S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response";
115
116    Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
117    Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
118    Es_F, AccessPermission:Read_Write,  desc="Es, other cluster read, filling";
119    E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling";
120    E1_F, AccessPermission:Read_Write, desc="...";
121    E0_Es, AccessPermission:Read_Write, desc="...";
122    E1_Es, AccessPermission:Read_Write, desc="...";
123    Ms_F0, AccessPermission:Read_Write, desc="...";
124    Ms_F1, AccessPermission:Read_Write, desc="...";
125    Ms_F, AccessPermission:Read_Write,  desc="...";
126    M0_F, AccessPermission:Read_Write, desc="...";
127    M0_Ms, AccessPermission:Read_Write, desc="...";
128    M1_F, AccessPermission:Read_Write, desc="...";
129    M1_Ms, AccessPermission:Read_Write, desc="...";
130
131    I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback";
132    S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
133    S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
134    S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck";
135
136  } // END STATES
137
138  // BEGIN EVENTS
139  enumeration(Event, desc="CP Events") {
140    // CP Initiated events
141    C0_Load_L1miss,            desc="Cluster 0 load, L1 missed";
142    C0_Load_L1hit,             desc="Cluster 0 load, L1 hit";
143    C1_Load_L1miss,            desc="Cluster 1 load L1 missed";
144    C1_Load_L1hit,             desc="Cluster 1 load L1 hit";
145    Ifetch0_L1hit,             desc="Instruction fetch, hit in the L1";
146    Ifetch1_L1hit,             desc="Instruction fetch, hit in the L1";
147    Ifetch0_L1miss,            desc="Instruction fetch, missed in the L1";
148    Ifetch1_L1miss,            desc="Instruction fetch, missed in the L1";
149    C0_Store_L1miss,           desc="Cluster 0 store missed in L1";
150    C0_Store_L1hit,            desc="Cluster 0 store hit in L1";
151    C1_Store_L1miss,           desc="Cluster 1 store missed in L1";
152    C1_Store_L1hit,            desc="Cluster 1 store hit in L1";
153    // NB Initiated events
154    NB_AckS,             desc="NB Ack to Core Request";
155    NB_AckM,             desc="NB Ack to Core Request";
156    NB_AckE,             desc="NB Ack to Core Request";
157
158    NB_AckWB,            desc="NB Ack for writeback";
159
160    // Memory System initiatied events
161    L1I_Repl,           desc="Replace address from L1I"; // Presumed clean
162    L1D0_Repl,           desc="Replace address from L1D0"; // Presumed clean
163    L1D1_Repl,           desc="Replace address from L1D1"; // Presumed clean
164    L2_Repl,            desc="Replace address from L2";
165
166    L2_to_L1D0,           desc="L1 fill from L2";
167    L2_to_L1D1,           desc="L1 fill from L2";
168    L2_to_L1I,           desc="L1 fill from L2";
169
170    // Probe Events
171    PrbInvData,         desc="probe, return O or M data";
172    PrbInvDataDemand,     desc="probe, return O or M data. Demand request";
173    PrbInv,             desc="probe, no need for data";
174    PrbShrData,         desc="probe downgrade, return O or M data";
175    PrbShrDataDemand,     desc="probe downgrade, return O or M data. Demand request";
176    ForceRepl,          desc="probe from r-buf. Act as though a repl";
177    ForceDowngrade,     desc="probe from r-buf. Act as though a repl";
178
179  }  // END EVENTS
180
181  enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
182    L1D0DataArrayRead,    desc="Read the data array";
183    L1D0DataArrayWrite,   desc="Write the data array";
184    L1D0TagArrayRead,     desc="Read the data array";
185    L1D0TagArrayWrite,    desc="Write the data array";
186    L1D1DataArrayRead,    desc="Read the data array";
187    L1D1DataArrayWrite,   desc="Write the data array";
188    L1D1TagArrayRead,     desc="Read the data array";
189    L1D1TagArrayWrite,    desc="Write the data array";
190    L1IDataArrayRead,     desc="Read the data array";
191    L1IDataArrayWrite,    desc="Write the data array";
192    L1ITagArrayRead,      desc="Read the data array";
193    L1ITagArrayWrite,     desc="Write the data array";
194    L2DataArrayRead,      desc="Read the data array";
195    L2DataArrayWrite,     desc="Write the data array";
196    L2TagArrayRead,       desc="Read the data array";
197    L2TagArrayWrite,      desc="Write the data array";
198  }
199
200
201  // BEGIN STRUCTURE DEFINITIONS
202
203
204  // Cache Entry
205  structure(Entry, desc="...", interface="AbstractCacheEntry") {
206    State CacheState,           desc="cache state";
207    bool Dirty,                 desc="Is the data dirty (diff than memory)?";
208    DataBlock DataBlk,          desc="data for the block";
209    bool FromL2, default="false", desc="block just moved from L2";
210  }
211
212  structure(TBE, desc="...") {
213    State TBEState,             desc="Transient state";
214    DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
215    bool Dirty,              desc="Is the data dirty (different than memory)?";
216    int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
217    bool Shared,             desc="Victim hit by shared probe";
218    bool AckNeeded,          desc="True if need to ack r-dir";
219   }
220
221  structure(TBETable, external="yes") {
222    TBE lookup(Addr);
223    void allocate(Addr);
224    void deallocate(Addr);
225    bool isPresent(Addr);
226  }
227
228  TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
229
230  Tick clockEdge();
231  Tick cyclesToTicks(Cycles c);
232
233  void set_cache_entry(AbstractCacheEntry b);
234  void unset_cache_entry();
235  void set_tbe(TBE b);
236  void unset_tbe();
237  void wakeUpAllBuffers();
238  void wakeUpBuffers(Addr a);
239  Cycles curCycle();
240  MachineID mapAddressToMachine(Addr addr, MachineType mtype);
241
242  // END STRUCTURE DEFINITIONS
243
244  // BEGIN INTERNAL FUNCTIONS
245
246  MachineID getPeer(MachineID mach) {
247    return createMachineID(MachineType:RegionBuffer, intToID(regionBufferNum));
248  }
249
250  bool addressInCore(Addr addr) {
251    return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr));
252  }
253
254  Entry getCacheEntry(Addr address), return_by_pointer="yes" {
255    Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
256    return L2cache_entry;
257  }
258
259  DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
260    TBE tbe := TBEs.lookup(addr);
261    if(is_valid(tbe)) {
262      return tbe.DataBlk;
263    } else {
264      return getCacheEntry(addr).DataBlk;
265    }
266  }
267
268  Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" {
269    if (cluster == 0) {
270      Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr));
271      return L1D0_entry;
272    } else {
273      Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr));
274      return L1D1_entry;
275    }
276  }
277
278  Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
279    Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
280    return c_entry;
281  }
282
283  bool presentOrAvail2(Addr addr) {
284    return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
285  }
286
287  bool presentOrAvailI(Addr addr) {
288    return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr);
289  }
290
291  bool presentOrAvailD0(Addr addr) {
292    return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr);
293  }
294
295  bool presentOrAvailD1(Addr addr) {
296    return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr);
297  }
298
299  State getState(TBE tbe, Entry cache_entry, Addr addr) {
300    if(is_valid(tbe)) {
301      return tbe.TBEState;
302    } else if (is_valid(cache_entry)) {
303      return cache_entry.CacheState;
304    }
305    return State:I;
306  }
307
308  void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
309    if (is_valid(tbe)) {
310      tbe.TBEState := state;
311    }
312
313    if (is_valid(cache_entry)) {
314      cache_entry.CacheState := state;
315    }
316  }
317
318  AccessPermission getAccessPermission(Addr addr) {
319    TBE tbe := TBEs.lookup(addr);
320    if(is_valid(tbe)) {
321      return CorePair_State_to_permission(tbe.TBEState);
322    }
323
324    Entry cache_entry := getCacheEntry(addr);
325    if(is_valid(cache_entry)) {
326      return CorePair_State_to_permission(cache_entry.CacheState);
327    }
328
329    return AccessPermission:NotPresent;
330  }
331
332  void functionalRead(Addr addr, Packet *pkt) {
333    TBE tbe := TBEs.lookup(addr);
334    if(is_valid(tbe)) {
335      testAndRead(addr, tbe.DataBlk, pkt);
336    } else {
337      functionalMemoryRead(pkt);
338    }
339  }
340
341  int functionalWrite(Addr addr, Packet *pkt) {
342    int num_functional_writes := 0;
343
344    TBE tbe := TBEs.lookup(addr);
345    if(is_valid(tbe)) {
346      num_functional_writes := num_functional_writes +
347            testAndWrite(addr, tbe.DataBlk, pkt);
348    }
349
350    num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
351    return num_functional_writes;
352  }
353
354  bool isValid(Addr addr) {
355      AccessPermission perm := getAccessPermission(addr);
356      if (perm == AccessPermission:NotPresent ||
357          perm == AccessPermission:Invalid ||
358          perm == AccessPermission:Busy) {
359          return false;
360      } else {
361          return true;
362      }
363  }
364
365  void setAccessPermission(Entry cache_entry, Addr addr, State state) {
366    if (is_valid(cache_entry)) {
367      cache_entry.changePermission(CorePair_State_to_permission(state));
368    }
369  }
370
371  MachineType testAndClearLocalHit(Entry cache_entry) {
372    assert(is_valid(cache_entry));
373    if (cache_entry.FromL2) {
374      cache_entry.FromL2 := false;
375      return MachineType:L2Cache;
376    } else {
377      return MachineType:L1Cache;
378    }
379  }
380
381  void recordRequestType(RequestType request_type, Addr addr) {
382    if (request_type == RequestType:L1D0DataArrayRead) {
383      L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
384    } else if (request_type == RequestType:L1D0DataArrayWrite) {
385      L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
386    } else if (request_type == RequestType:L1D0TagArrayRead) {
387      L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
388    } else if (request_type == RequestType:L1D0TagArrayWrite) {
389      L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
390    } else if (request_type == RequestType:L1D1DataArrayRead) {
391      L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
392    } else if (request_type == RequestType:L1D1DataArrayWrite) {
393      L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
394    } else if (request_type == RequestType:L1D1TagArrayRead) {
395      L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
396    } else if (request_type == RequestType:L1D1TagArrayWrite) {
397      L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
398    } else if (request_type == RequestType:L1IDataArrayRead) {
399      L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr);
400    } else if (request_type == RequestType:L1IDataArrayWrite) {
401      L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
402    } else if (request_type == RequestType:L1ITagArrayRead) {
403      L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr);
404    } else if (request_type == RequestType:L1ITagArrayWrite) {
405      L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
406    } else if (request_type == RequestType:L2DataArrayRead) {
407      L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
408    } else if (request_type == RequestType:L2DataArrayWrite) {
409      L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
410    } else if (request_type == RequestType:L2TagArrayRead) {
411      L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
412    } else if (request_type == RequestType:L2TagArrayWrite) {
413      L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
414    }
415  }
416
417  bool checkResourceAvailable(RequestType request_type, Addr addr) {
418    if (request_type == RequestType:L2DataArrayRead) {
419      return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
420    } else if (request_type == RequestType:L2DataArrayWrite) {
421      return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
422    } else if (request_type == RequestType:L2TagArrayRead) {
423      return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
424    } else if (request_type == RequestType:L2TagArrayWrite) {
425      return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
426    } else if  (request_type == RequestType:L1D0DataArrayRead) {
427      return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
428    } else if  (request_type == RequestType:L1D0DataArrayWrite) {
429      return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
430    } else if (request_type == RequestType:L1D0TagArrayRead) {
431      return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
432    } else if (request_type == RequestType:L1D0TagArrayWrite) {
433      return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
434    } else if (request_type == RequestType:L1D1DataArrayRead) {
435      return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
436    } else if (request_type == RequestType:L1D1DataArrayWrite) {
437      return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
438    } else if (request_type == RequestType:L1D1TagArrayRead) {
439      return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
440    } else if (request_type == RequestType:L1D1TagArrayWrite) {
441      return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
442    } else if (request_type == RequestType:L1IDataArrayRead) {
443      return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
444    } else if (request_type == RequestType:L1IDataArrayWrite) {
445      return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
446    } else if (request_type == RequestType:L1ITagArrayRead) {
447      return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
448    } else if (request_type == RequestType:L1ITagArrayWrite) {
449      return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
450    } else {
451      return true;
452    }
453  }
454
455  // END INTERNAL FUNCTIONS
456
457  // ** OUT_PORTS **
458
459  out_port(requestNetwork_out, CPURequestMsg, requestFromCore);
460  out_port(responseNetwork_out, ResponseMsg, responseFromCore);
461  out_port(triggerQueue_out, TriggerMsg, triggerQueue);
462  out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
463
464  // ** IN_PORTS **
465
466  in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") {
467    if (triggerQueue_in.isReady(clockEdge())) {
468      peek(triggerQueue_in, TriggerMsg) {
469        Entry cache_entry := getCacheEntry(in_msg.addr);
470        TBE tbe := TBEs.lookup(in_msg.addr);
471
472        if (in_msg.Type == TriggerType:L2_to_L1) {
473          if (in_msg.Dest == CacheId:L1I) {
474            trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe);
475          } else if (in_msg.Dest == CacheId:L1D0) {
476            trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe);
477          } else if (in_msg.Dest == CacheId:L1D1) {
478            trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe);
479          } else {
480            error("unexpected trigger dest");
481          }
482        }
483      }
484    }
485  }
486
487
488  in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) {
489    if (probeNetwork_in.isReady(clockEdge())) {
490      peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") {
491        Entry cache_entry := getCacheEntry(in_msg.addr);
492        TBE tbe := TBEs.lookup(in_msg.addr);
493
494        if (in_msg.Type == ProbeRequestType:PrbInv) {
495          if (in_msg.DemandRequest) {
496            trigger(Event:PrbInvDataDemand, in_msg.addr, cache_entry, tbe);
497          } else if (in_msg.ReturnData) {
498            trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
499          } else {
500            trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
501          }
502        } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
503          if (in_msg.DemandRequest) {
504               trigger(Event:PrbShrDataDemand, in_msg.addr, cache_entry, tbe);
505          } else {
506               assert(in_msg.ReturnData);
507               trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
508          }
509        } else if (in_msg.Type == ProbeRequestType:PrbRepl) {
510          trigger(Event:ForceRepl, in_msg.addr, cache_entry, tbe);
511        } else if (in_msg.Type == ProbeRequestType:PrbRegDowngrade) {
512          trigger(Event:ForceDowngrade, in_msg.addr, cache_entry, tbe);
513        } else {
514          error("Unknown probe request");
515        }
516      }
517    }
518  }
519
520
521  // ResponseNetwork
522  in_port(responseToCore_in, ResponseMsg, responseToCore) {
523    if (responseToCore_in.isReady(clockEdge())) {
524      peek(responseToCore_in, ResponseMsg, block_on="addr") {
525
526        Entry cache_entry := getCacheEntry(in_msg.addr);
527        TBE tbe := TBEs.lookup(in_msg.addr);
528
529        if (in_msg.Type == CoherenceResponseType:NBSysResp) {
530          if (in_msg.State == CoherenceState:Modified) {
531              trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe);
532          } else if (in_msg.State == CoherenceState:Shared) {
533            trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe);
534          } else if (in_msg.State == CoherenceState:Exclusive) {
535            trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe);
536          }
537        } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
538          trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe);
539        } else {
540          error("Unexpected Response Message to Core");
541        }
542      }
543    }
544  }
545
546  // Nothing from the Unblock Network
547
548  // Mandatory Queue
549  in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
550    if (mandatoryQueue_in.isReady(clockEdge())) {
551      peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
552
553        Entry cache_entry := getCacheEntry(in_msg.LineAddress);
554        TBE tbe := TBEs.lookup(in_msg.LineAddress);
555
556        if (in_msg.Type == RubyRequestType:IFETCH) {
557          // FETCH ACCESS
558
559          if (L1Icache.isTagPresent(in_msg.LineAddress)) {
560            if (mod(in_msg.contextId, 2) == 0) {
561              trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe);
562            } else {
563              trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe);
564            }
565          } else {
566            if (presentOrAvail2(in_msg.LineAddress)) {
567              if (presentOrAvailI(in_msg.LineAddress)) {
568                if (mod(in_msg.contextId, 2) == 0) {
569                  trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry,
570                          tbe);
571                } else {
572                  trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry,
573                          tbe);
574                }
575              } else {
576                Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
577                trigger(Event:L1I_Repl, victim,
578                        getCacheEntry(victim), TBEs.lookup(victim));
579              }
580            } else { // Not present or avail in L2
581              Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
582              DPRINTF(RubySlicc, "Victim for %s L2_Repl(0) is %s\n", in_msg.LineAddress, victim);
583              trigger(Event:L2_Repl, victim, getCacheEntry(victim),
584                      TBEs.lookup(victim));
585            }
586          }
587        } else {
588          // DATA ACCESS
589          if (mod(in_msg.contextId, 2) == 1) {
590            if (L1D1cache.isTagPresent(in_msg.LineAddress)) {
591              if (in_msg.Type == RubyRequestType:LD) {
592                trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry,
593                        tbe);
594              } else {
595                // Stores must write through, make sure L2 avail.
596                if (presentOrAvail2(in_msg.LineAddress)) {
597                  trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry,
598                          tbe);
599                } else {
600                  Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
601              DPRINTF(RubySlicc, "Victim for %s L2_Repl(1) is %s\n", in_msg.LineAddress, victim);
602                  trigger(Event:L2_Repl, victim, getCacheEntry(victim),
603                          TBEs.lookup(victim));
604                }
605              }
606            } else {
607              if (presentOrAvail2(in_msg.LineAddress)) {
608                if (presentOrAvailD1(in_msg.LineAddress)) {
609                  if (in_msg.Type == RubyRequestType:LD) {
610                    trigger(Event:C1_Load_L1miss, in_msg.LineAddress,
611                            cache_entry, tbe);
612                  } else {
613                    trigger(Event:C1_Store_L1miss, in_msg.LineAddress,
614                            cache_entry, tbe);
615                  }
616                } else {
617                  Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
618              DPRINTF(RubySlicc, "Victim for %s L1D1_Repl is %s\n", in_msg.LineAddress, victim);
619                  trigger(Event:L1D1_Repl, victim,
620                          getCacheEntry(victim), TBEs.lookup(victim));
621                }
622              } else { // not present or avail in L2
623                Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
624              DPRINTF(RubySlicc, "Victim for %s L2_Repl(2) is %s\n", in_msg.LineAddress, victim);
625                trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
626              }
627            }
628          } else {
629            Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0);
630            if (is_valid(L1D0cache_entry)) {
631              if (in_msg.Type == RubyRequestType:LD) {
632                trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry,
633                    tbe);
634              } else {
635                if (presentOrAvail2(in_msg.LineAddress)) {
636                  trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry,
637                      tbe);
638                } else {
639                  Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
640              DPRINTF(RubySlicc, "Victim for %s L2_Repl(3) is %s\n", in_msg.LineAddress, victim);
641                  trigger(Event:L2_Repl, victim, getCacheEntry(victim),
642                      TBEs.lookup(victim));
643                }
644              }
645            } else {
646              if (presentOrAvail2(in_msg.LineAddress)) {
647                if (presentOrAvailD0(in_msg.LineAddress)) {
648                  if (in_msg.Type == RubyRequestType:LD) {
649                    trigger(Event:C0_Load_L1miss, in_msg.LineAddress,
650                        cache_entry, tbe);
651                  } else {
652                    trigger(Event:C0_Store_L1miss, in_msg.LineAddress,
653                            cache_entry, tbe);
654                  }
655                } else {
656                  Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
657              DPRINTF(RubySlicc, "Victim for %s L1D0_Repl is %s\n", in_msg.LineAddress, victim);
658                  trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
659                          TBEs.lookup(victim));
660                }
661              } else {
662                Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
663              DPRINTF(RubySlicc, "Victim for %s L2_Repl(4) is %s\n", in_msg.LineAddress, victim);
664                trigger(Event:L2_Repl, victim, getCacheEntry(victim),
665                        TBEs.lookup(victim));
666              }
667            }
668          }
669        }
670      }
671    }
672  }
673
674
675  // ACTIONS
676  action(ii_invIcache, "ii", desc="invalidate iCache") {
677    if (L1Icache.isTagPresent(address)) {
678      L1Icache.deallocate(address);
679    }
680  }
681
682  action(i0_invCluster, "i0", desc="invalidate cluster 0") {
683    if (L1D0cache.isTagPresent(address)) {
684      L1D0cache.deallocate(address);
685    }
686  }
687
688  action(i1_invCluster, "i1", desc="invalidate cluster 1") {
689    if (L1D1cache.isTagPresent(address)) {
690      L1D1cache.deallocate(address);
691    }
692  }
693
694  action(ib_invBothClusters, "ib", desc="invalidate both clusters") {
695    if (L1D0cache.isTagPresent(address)) {
696      L1D0cache.deallocate(address);
697    }
698    if (L1D1cache.isTagPresent(address)) {
699      L1D1cache.deallocate(address);
700    }
701  }
702
703  action(i2_invL2, "i2", desc="invalidate L2") {
704    if(is_valid(cache_entry)) {
705        L2cache.deallocate(address);
706    }
707    unset_cache_entry();
708  }
709
710  action(n_issueRdBlk, "n", desc="Issue RdBlk") {
711    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
712      out_msg.addr := address;
713      out_msg.Type := CoherenceRequestType:RdBlk;
714      out_msg.Requestor := machineID;
715      out_msg.Destination.add(getPeer(machineID));
716      out_msg.MessageSize := MessageSizeType:Request_Control;
717      out_msg.InitialRequestTime := curCycle();
718    }
719  }
720
721  action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") {
722    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
723      out_msg.addr := address;
724      out_msg.Type := CoherenceRequestType:RdBlkM;
725      out_msg.Requestor := machineID;
726      out_msg.Destination.add(getPeer(machineID));
727      out_msg.MessageSize := MessageSizeType:Request_Control;
728      out_msg.InitialRequestTime := curCycle();
729    }
730  }
731
732  action(nMs_issueRdBlkMSinked, "nMs", desc="Issue RdBlkM with CtoDSinked") {
733    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
734      out_msg.addr := address;
735      out_msg.Type := CoherenceRequestType:RdBlkM;
736      out_msg.Requestor := machineID;
737      out_msg.Destination.add(getPeer(machineID));
738      out_msg.MessageSize := MessageSizeType:Request_Control;
739      out_msg.CtoDSinked := true;
740    }
741  }
742
743  action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
744    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
745      out_msg.addr := address;
746      out_msg.Type := CoherenceRequestType:RdBlkS;
747      out_msg.Requestor := machineID;
748      out_msg.Destination.add(getPeer(machineID));
749      out_msg.MessageSize := MessageSizeType:Request_Control;
750      out_msg.InitialRequestTime := curCycle();
751    }
752  }
753
754  action(nSs_issueRdBlkSSinked, "nSs", desc="Issue RdBlkS with CtoDSinked") {
755    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
756      out_msg.addr := address;
757      out_msg.Type := CoherenceRequestType:RdBlkS;
758      out_msg.Requestor := machineID;
759      out_msg.Destination.add(getPeer(machineID));
760      out_msg.CtoDSinked := true;
761      out_msg.MessageSize := MessageSizeType:Request_Control;
762    }
763  }
764
765  action(vd_victim, "vd", desc="Victimize M/O L2 Data") {
766    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
767      out_msg.addr := address;
768      out_msg.Requestor := machineID;
769      assert(is_valid(cache_entry));
770      out_msg.DataBlk := cache_entry.DataBlk;
771      assert(cache_entry.Dirty);
772      out_msg.Destination.add(getPeer(machineID));
773      out_msg.MessageSize := MessageSizeType:Request_Control;
774      out_msg.Type := CoherenceRequestType:VicDirty;
775      out_msg.InitialRequestTime := curCycle();
776      if (cache_entry.CacheState == State:O) {
777        out_msg.Shared := true;
778      } else {
779        out_msg.Shared := false;
780      }
781    }
782  }
783
784  action(vc_victim, "vc", desc="Victimize E/S L2 Data") {
785    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
786      out_msg.addr := address;
787      out_msg.Requestor := machineID;
788      out_msg.Destination.add(getPeer(machineID));
789      out_msg.MessageSize := MessageSizeType:Request_Control;
790      out_msg.Type := CoherenceRequestType:VicClean;
791      out_msg.InitialRequestTime := curCycle();
792      if (cache_entry.CacheState == State:S) {
793        out_msg.Shared := true;
794      } else {
795        out_msg.Shared := false;
796      }
797    }
798  }
799
800  // Could send these two directly to dir if we made a new out network on channel 0
801  action(vdf_victimForce, "vdf", desc="Victimize M/O L2 Data") {
802    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
803      out_msg.addr := address;
804      out_msg.Requestor := machineID;
805      assert(is_valid(cache_entry));
806      out_msg.DataBlk := cache_entry.DataBlk;
807      assert(cache_entry.Dirty);
808      out_msg.Destination.add(getPeer(machineID));
809      out_msg.MessageSize := MessageSizeType:Request_Control;
810      out_msg.Type := CoherenceRequestType:VicDirty;
811      out_msg.InitialRequestTime := curCycle();
812      if (cache_entry.CacheState == State:O) {
813        out_msg.Shared := true;
814      } else {
815        out_msg.Shared := false;
816      }
817      out_msg.Private := true;
818    }
819  }
820
821  action(vcf_victimForce, "vcf", desc="Victimize E/S L2 Data") {
822    enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
823      out_msg.addr := address;
824      out_msg.Requestor := machineID;
825      out_msg.Destination.add(getPeer(machineID));
826      out_msg.MessageSize := MessageSizeType:Request_Control;
827      out_msg.Type := CoherenceRequestType:VicClean;
828      out_msg.InitialRequestTime := curCycle();
829      if (cache_entry.CacheState == State:S) {
830        out_msg.Shared := true;
831      } else {
832        out_msg.Shared := false;
833      }
834      out_msg.Private := true;
835    }
836  }
837
838  action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
839    if (L1D0cache.isTagPresent(address) == false) {
840      L1D0cache.allocateVoid(address, new Entry);
841    }
842  }
843
844  action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
845    if (L1D1cache.isTagPresent(address) == false) {
846      L1D1cache.allocateVoid(address, new Entry);
847    }
848  }
849
850  action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
851    if (L1Icache.isTagPresent(address) == false) {
852      L1Icache.allocateVoid(address, new Entry);
853    }
854  }
855
856  action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
857    if (is_invalid(cache_entry)) {
858      set_cache_entry(L2cache.allocate(address, new Entry));
859    }
860  }
861
862  action(t_allocateTBE, "t", desc="allocate TBE Entry") {
863    check_allocate(TBEs);
864    assert(is_valid(cache_entry));
865    TBEs.allocate(address);
866    set_tbe(TBEs.lookup(address));
867    tbe.DataBlk := cache_entry.DataBlk;  // Data only used for WBs
868    tbe.Dirty := cache_entry.Dirty;
869    tbe.Shared := false;
870  }
871
872  action(d_deallocateTBE, "d", desc="Deallocate TBE") {
873    TBEs.deallocate(address);
874    unset_tbe();
875  }
876
877  action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
878    mandatoryQueue_in.dequeue(clockEdge());
879  }
880
881  action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
882    responseToCore_in.dequeue(clockEdge());
883  }
884
885  action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") {
886    triggerQueue_in.dequeue(clockEdge());
887  }
888
889  action(pp_popProbeQueue, "pp", desc="pop probe queue") {
890    probeNetwork_in.dequeue(clockEdge());
891  }
892
893  action(il0_loadDone, "il0", desc="Cluster 0 i load done") {
894    Entry entry := getICacheEntry(address);
895    Entry l2entry := getCacheEntry(address); // Used for functional accesses
896    assert(is_valid(entry));
897    // L2 supplies data (functional accesses only look in L2, ok because L1
898    //                   writes through to L2)
899    sequencer.readCallback(address,
900                           l2entry.DataBlk,
901                           true,
902                           testAndClearLocalHit(entry));
903  }
904
905  action(il1_loadDone, "il1", desc="Cluster 1 i load done") {
906    Entry entry := getICacheEntry(address);
907    Entry l2entry := getCacheEntry(address); // Used for functional accesses
908    assert(is_valid(entry));
909    // L2 supplies data (functional accesses only look in L2, ok because L1
910    //                   writes through to L2)
911    sequencer1.readCallback(address,
912                            l2entry.DataBlk,
913                            true,
914                            testAndClearLocalHit(entry));
915  }
916
917  action(l0_loadDone, "l0", desc="Cluster 0 load done") {
918    Entry entry := getL1CacheEntry(address, 0);
919    Entry l2entry := getCacheEntry(address); // Used for functional accesses
920    assert(is_valid(entry));
921    // L2 supplies data (functional accesses only look in L2, ok because L1
922    //                   writes through to L2)
923    sequencer.readCallback(address,
924                           l2entry.DataBlk,
925                           true,
926                           testAndClearLocalHit(entry));
927  }
928
929  action(l1_loadDone, "l1", desc="Cluster 1 load done") {
930    Entry entry := getL1CacheEntry(address, 1);
931    Entry l2entry := getCacheEntry(address); // Used for functional accesses
932    assert(is_valid(entry));
933    // L2 supplies data (functional accesses only look in L2, ok because L1
934    //                   writes through to L2)
935    sequencer1.readCallback(address,
936                            l2entry.DataBlk,
937                            true,
938                            testAndClearLocalHit(entry));
939  }
940
941  action(xl0_loadDone, "xl0", desc="Cluster 0 load done") {
942    peek(responseToCore_in, ResponseMsg) {
943      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
944              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
945      Entry l2entry := getCacheEntry(address); // Used for functional accesses
946      DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n",
947              address, l2entry.DataBlk);
948      // L2 supplies data (functional accesses only look in L2, ok because L1
949      //                   writes through to L2)
950      assert(is_valid(l2entry));
951      sequencer.readCallback(address,
952                             l2entry.DataBlk,
953                             false,
954                             machineIDToMachineType(in_msg.Sender),
955                             in_msg.InitialRequestTime,
956                             in_msg.ForwardRequestTime,
957                             in_msg.ProbeRequestStartTime);
958    }
959  }
960
961  action(xl1_loadDone, "xl1", desc="Cluster 1 load done") {
962   peek(responseToCore_in, ResponseMsg) {
963      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
964              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
965      Entry l2entry := getCacheEntry(address); // Used for functional accesses
966      // L2 supplies data (functional accesses only look in L2, ok because L1
967      //                   writes through to L2)
968      assert(is_valid(l2entry));
969      sequencer1.readCallback(address,
970                              l2entry.DataBlk,
971                              false,
972                              machineIDToMachineType(in_msg.Sender),
973                              in_msg.InitialRequestTime,
974                              in_msg.ForwardRequestTime,
975                              in_msg.ProbeRequestStartTime);
976   }
977  }
978
979  action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") {
980    peek(responseToCore_in, ResponseMsg) {
981      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
982              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
983      Entry l2entry := getCacheEntry(address); // Used for functional accesses
984      // L2 supplies data (functional accesses only look in L2, ok because L1
985      //                   writes through to L2)
986      assert(is_valid(l2entry));
987      sequencer.readCallback(address,
988                             l2entry.DataBlk,
989                             false,
990                             machineIDToMachineType(in_msg.Sender),
991                             in_msg.InitialRequestTime,
992                             in_msg.ForwardRequestTime,
993                             in_msg.ProbeRequestStartTime);
994    }
995  }
996
997  action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") {
998    peek(responseToCore_in, ResponseMsg) {
999      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1000              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1001      Entry l2entry := getCacheEntry(address); // Used for functional accesses
1002      // L2 supplies data (functional accesses only look in L2, ok because L1
1003      //                   writes through to L2)
1004      assert(is_valid(l2entry));
1005      sequencer1.readCallback(address,
1006                              l2entry.DataBlk,
1007                              false,
1008                              machineIDToMachineType(in_msg.Sender),
1009                              in_msg.InitialRequestTime,
1010                              in_msg.ForwardRequestTime,
1011                              in_msg.ProbeRequestStartTime);
1012    }
1013  }
1014
1015  action(s0_storeDone, "s0", desc="Cluster 0 store done") {
1016    Entry entry := getL1CacheEntry(address, 0);
1017    assert(is_valid(entry));
1018    assert(is_valid(cache_entry));
1019    sequencer.writeCallback(address,
1020                            cache_entry.DataBlk,
1021                            true,
1022                            testAndClearLocalHit(entry));
1023    cache_entry.Dirty := true;
1024    entry.DataBlk := cache_entry.DataBlk;
1025    entry.Dirty := true;
1026    DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1027  }
1028
1029  action(s1_storeDone, "s1", desc="Cluster 1 store done") {
1030    Entry entry := getL1CacheEntry(address, 1);
1031    assert(is_valid(entry));
1032    assert(is_valid(cache_entry));
1033    sequencer1.writeCallback(address,
1034                             cache_entry.DataBlk,
1035                             true,
1036                             testAndClearLocalHit(entry));
1037    cache_entry.Dirty := true;
1038    entry.Dirty := true;
1039    entry.DataBlk := cache_entry.DataBlk;
1040    DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1041  }
1042
1043  action(xs0_storeDone, "xs0", desc="Cluster 0 store done") {
1044    peek(responseToCore_in, ResponseMsg) {
1045      Entry entry := getL1CacheEntry(address, 0);
1046      assert(is_valid(entry));
1047      assert(is_valid(cache_entry));
1048      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1049             (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1050      sequencer.writeCallback(address,
1051                              cache_entry.DataBlk,
1052                              false,
1053                              machineIDToMachineType(in_msg.Sender),
1054                              in_msg.InitialRequestTime,
1055                              in_msg.ForwardRequestTime,
1056                              in_msg.ProbeRequestStartTime);
1057      cache_entry.Dirty := true;
1058      entry.Dirty := true;
1059      entry.DataBlk := cache_entry.DataBlk;
1060      DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1061    }
1062  }
1063
1064  action(xs1_storeDone, "xs1", desc="Cluster 1 store done") {
1065    peek(responseToCore_in, ResponseMsg) {
1066      Entry entry := getL1CacheEntry(address, 1);
1067      assert(is_valid(entry));
1068      assert(is_valid(cache_entry));
1069      assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1070             (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1071      sequencer1.writeCallback(address,
1072                               cache_entry.DataBlk,
1073                               false,
1074                               machineIDToMachineType(in_msg.Sender),
1075                               in_msg.InitialRequestTime,
1076                               in_msg.ForwardRequestTime,
1077                               in_msg.ProbeRequestStartTime);
1078      cache_entry.Dirty := true;
1079      entry.Dirty := true;
1080      entry.DataBlk := cache_entry.DataBlk;
1081      DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1082    }
1083  }
1084
1085  action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") {
1086    if (send_evictions) {
1087      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1088      sequencer.evictionCallback(address);
1089    }
1090  }
1091
1092  action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") {
1093    if (send_evictions) {
1094      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1095      sequencer1.evictionCallback(address);
1096    }
1097  }
1098
1099  action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") {
1100    Entry entry := getICacheEntry(address);
1101    assert(is_valid(entry));
1102    assert(is_valid(cache_entry));
1103    entry.Dirty := cache_entry.Dirty;
1104    entry.DataBlk := cache_entry.DataBlk;
1105    entry.FromL2 := true;
1106  }
1107
1108  action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") {
1109    Entry entry := getL1CacheEntry(address, 0);
1110    assert(is_valid(entry));
1111    assert(is_valid(cache_entry));
1112    entry.Dirty := cache_entry.Dirty;
1113    entry.DataBlk := cache_entry.DataBlk;
1114    entry.FromL2 := true;
1115  }
1116
1117  action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
1118    peek(responseToCore_in, ResponseMsg) {
1119      enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1120        out_msg.addr := address;
1121        out_msg.Type := CoherenceResponseType:StaleNotif;
1122        out_msg.Sender := machineID;
1123        out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1124        out_msg.MessageSize := MessageSizeType:Response_Control;
1125        DPRINTF(RubySlicc, "%s\n", out_msg);
1126      }
1127    }
1128  }
1129
1130  action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") {
1131    Entry entry := getL1CacheEntry(address, 1);
1132    assert(is_valid(entry));
1133    assert(is_valid(cache_entry));
1134    entry.Dirty := cache_entry.Dirty;
1135    entry.DataBlk := cache_entry.DataBlk;
1136    entry.FromL2 := true;
1137  }
1138
1139  action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") {
1140    enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1141      out_msg.addr := address;
1142      out_msg.Type := TriggerType:L2_to_L1;
1143      out_msg.Dest := CacheId:L1I;
1144    }
1145  }
1146
1147  action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") {
1148    enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1149      out_msg.addr := address;
1150      out_msg.Type := TriggerType:L2_to_L1;
1151      out_msg.Dest := CacheId:L1D0;
1152    }
1153  }
1154
1155  action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") {
1156    enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1157      out_msg.addr := address;
1158      out_msg.Type := TriggerType:L2_to_L1;
1159      out_msg.Dest := CacheId:L1D1;
1160    }
1161  }
1162
1163  action(wi_writeIcache, "wi", desc="write data to icache (and l2)") {
1164    peek(responseToCore_in, ResponseMsg) {
1165      Entry entry := getICacheEntry(address);
1166      assert(is_valid(entry));
1167      assert(is_valid(cache_entry));
1168      entry.DataBlk := in_msg.DataBlk;
1169      entry.Dirty := in_msg.Dirty;
1170      cache_entry.DataBlk := in_msg.DataBlk;
1171      cache_entry.Dirty := in_msg.Dirty;
1172    }
1173  }
1174
1175  action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") {
1176    peek(responseToCore_in, ResponseMsg) {
1177      Entry entry := getL1CacheEntry(address, 0);
1178      assert(is_valid(entry));
1179      assert(is_valid(cache_entry));
1180      entry.DataBlk := in_msg.DataBlk;
1181      entry.Dirty := in_msg.Dirty;
1182      cache_entry.DataBlk := in_msg.DataBlk;
1183      cache_entry.Dirty := in_msg.Dirty;
1184    }
1185  }
1186
1187  action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") {
1188    peek(responseToCore_in, ResponseMsg) {
1189      Entry entry := getL1CacheEntry(address, 1);
1190      assert(is_valid(entry));
1191      assert(is_valid(cache_entry));
1192      entry.DataBlk := in_msg.DataBlk;
1193      entry.Dirty := in_msg.Dirty;
1194      cache_entry.DataBlk := in_msg.DataBlk;
1195      cache_entry.Dirty := in_msg.Dirty;
1196    }
1197  }
1198
1199  action(wb_data, "wb", desc="write back data") {
1200    peek(responseToCore_in, ResponseMsg) {
1201      enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1202        out_msg.addr := address;
1203        out_msg.Type := CoherenceResponseType:CPUData;
1204        out_msg.Sender := machineID;
1205        out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1206        out_msg.DataBlk := tbe.DataBlk;
1207        out_msg.Dirty := tbe.Dirty;
1208        if (tbe.Shared) {
1209          out_msg.NbReqShared := true;
1210        } else {
1211          out_msg.NbReqShared := false;
1212        }
1213        out_msg.State := CoherenceState:Shared; // faux info
1214        out_msg.MessageSize := MessageSizeType:Writeback_Data;
1215        DPRINTF(RubySlicc, "%s\n", out_msg);
1216      }
1217    }
1218  }
1219
1220  action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
1221    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1222      out_msg.addr := address;
1223      out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1224      out_msg.Sender := machineID;
1225      // will this always be ok? probably not for multisocket
1226      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1227      out_msg.Dirty := false;
1228      out_msg.Hit := false;
1229      out_msg.Ntsl := true;
1230      out_msg.State := CoherenceState:NA;
1231      out_msg.MessageSize := MessageSizeType:Response_Control;
1232      out_msg.isValid := isValid(address);
1233    }
1234  }
1235
1236  action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
1237    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1238      out_msg.addr := address;
1239      out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1240      out_msg.Sender := machineID;
1241      // will this always be ok? probably not for multisocket
1242      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1243      out_msg.Dirty := false;
1244      out_msg.Ntsl := true;
1245      out_msg.Hit := false;
1246      APPEND_TRANSITION_COMMENT("Setting Ms");
1247      out_msg.State := CoherenceState:NA;
1248      out_msg.MessageSize := MessageSizeType:Response_Control;
1249      out_msg.isValid := isValid(address);
1250    }
1251  }
1252
1253  action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") {
1254    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1255      out_msg.addr := address;
1256      out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1257      out_msg.Sender := machineID;
1258      // will this always be ok? probably not for multisocket
1259      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1260      assert(addressInCore(address) || is_valid(tbe));
1261      out_msg.Dirty := false;  // only true if sending back data i think
1262      out_msg.Hit := true;
1263      out_msg.Ntsl := false;
1264      out_msg.State := CoherenceState:NA;
1265      out_msg.MessageSize := MessageSizeType:Response_Control;
1266      out_msg.isValid := isValid(address);
1267    }
1268  }
1269
1270  action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") {
1271    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1272      out_msg.addr := address;
1273      out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1274      out_msg.Sender := machineID;
1275      // will this always be ok? probably not for multisocket
1276      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1277      if (addressInCore(address)) {
1278        out_msg.Hit := true;
1279      } else {
1280        out_msg.Hit := false;
1281      }
1282      out_msg.Dirty := false;  // not sending back data, so def. not dirty
1283      out_msg.Ntsl := false;
1284      out_msg.State := CoherenceState:NA;
1285      out_msg.MessageSize := MessageSizeType:Response_Control;
1286      out_msg.isValid := isValid(address);
1287    }
1288  }
1289
1290  action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
1291    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1292      assert(is_valid(cache_entry));
1293      out_msg.addr := address;
1294      out_msg.Type := CoherenceResponseType:CPUPrbResp;
1295      out_msg.Sender := machineID;
1296      // will this always be ok? probably not for multisocket
1297      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1298      out_msg.DataBlk := cache_entry.DataBlk;
1299      assert(cache_entry.Dirty);
1300      out_msg.Dirty := true;
1301      out_msg.Hit := true;
1302      out_msg.State := CoherenceState:NA;
1303      out_msg.MessageSize := MessageSizeType:Response_Data;
1304      out_msg.isValid := isValid(address);
1305    }
1306  }
1307
1308  action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
1309    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1310      assert(is_valid(cache_entry));
1311      out_msg.addr := address;
1312      out_msg.Type := CoherenceResponseType:CPUPrbResp;
1313      out_msg.Sender := machineID;
1314      // will this always be ok? probably not for multisocket
1315      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1316      out_msg.DataBlk := cache_entry.DataBlk;
1317      assert(cache_entry.Dirty);
1318      out_msg.Dirty := true;
1319      out_msg.Hit := true;
1320      APPEND_TRANSITION_COMMENT("Setting Ms");
1321      out_msg.State := CoherenceState:NA;
1322      out_msg.MessageSize := MessageSizeType:Response_Data;
1323      out_msg.isValid := isValid(address);
1324    }
1325  }
1326
1327  action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
1328    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1329      assert(is_valid(tbe));
1330      out_msg.addr := address;
1331      out_msg.Type := CoherenceResponseType:CPUPrbResp;
1332      out_msg.Sender := machineID;
1333      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1334      out_msg.DataBlk := tbe.DataBlk;
1335      assert(tbe.Dirty);
1336      out_msg.Dirty := true;
1337      out_msg.Hit := true;
1338      out_msg.State := CoherenceState:NA;
1339      out_msg.MessageSize := MessageSizeType:Response_Data;
1340      out_msg.isValid := isValid(address);
1341    }
1342  }
1343
1344  action(ra_sendReplAck, "ra", desc="Send ack to r-buf that line is replaced if needed") {
1345    if (is_invalid(tbe) || tbe.AckNeeded) {
1346      enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
1347        out_msg.addr := address;
1348        out_msg.Type := CoherenceRequestType:InvAck;
1349        out_msg.Requestor := machineID;
1350        out_msg.Destination.add(getPeer(machineID));
1351        out_msg.MessageSize := MessageSizeType:Request_Control;
1352      }
1353      APPEND_TRANSITION_COMMENT(" Sending ack to r-buf ");
1354    } else {
1355      APPEND_TRANSITION_COMMENT(" NOT Sending ack to r-buf ");
1356    }
1357  }
1358
1359  action(m_markAckNeeded, "m", desc="Mark TBE to send ack when deallocated") {
1360    assert(is_valid(tbe));
1361    tbe.AckNeeded := true;
1362  }
1363
1364  action(mc_cancelWB, "mc", desc="send writeback cancel to L3") {
1365    enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1366      out_msg.addr := address;
1367      out_msg.Type := CoherenceResponseType:CPUCancelWB;
1368      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1369      out_msg.Sender := machineID;
1370      out_msg.MessageSize := MessageSizeType:Response_Control;
1371    }
1372  }
1373
1374  action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") {
1375    assert(is_valid(tbe));
1376    tbe.Shared := true;
1377  }
1378
1379  action(uu_sendUnblock, "uu", desc="state changed, unblock") {
1380    enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
1381      out_msg.addr := address;
1382      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1383      out_msg.MessageSize := MessageSizeType:Unblock_Control;
1384      out_msg.wasValid := isValid(address);
1385      DPRINTF(RubySlicc, "%s\n", out_msg);
1386    }
1387  }
1388
1389  action(sdv_sendDoneValid, "sdv", desc="Request finished, send done ack") {
1390    enqueue(unblockNetwork_out, UnblockMsg, 1) {
1391      out_msg.addr := address;
1392      out_msg.Destination.add(getPeer(machineID));
1393      out_msg.DoneAck := true;
1394      out_msg.MessageSize := MessageSizeType:Unblock_Control;
1395      if (is_valid(tbe)) {
1396          out_msg.Dirty := tbe.Dirty;
1397      } else if (is_valid(cache_entry)) {
1398          out_msg.Dirty := cache_entry.Dirty;
1399      } else {
1400          out_msg.Dirty := false;
1401      }
1402      out_msg.validToInvalid := false;
1403      DPRINTF(RubySlicc, "%s\n", out_msg);
1404    }
1405  }
1406
1407  action(sdi_sendDoneInvalid, "sdi", desc="Request finished, send done ack") {
1408    enqueue(unblockNetwork_out, UnblockMsg, 1) {
1409      out_msg.addr := address;
1410      out_msg.Destination.add(getPeer(machineID));
1411      out_msg.DoneAck := true;
1412      out_msg.MessageSize := MessageSizeType:Unblock_Control;
1413      if (is_valid(tbe)) {
1414          out_msg.Dirty := tbe.Dirty;
1415      } else if (is_valid(cache_entry)) {
1416          out_msg.Dirty := cache_entry.Dirty;
1417      } else {
1418          out_msg.Dirty := false;
1419      }
1420      out_msg.validToInvalid := true;
1421      DPRINTF(RubySlicc, "%s\n", out_msg);
1422    }
1423  }
1424
1425  action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
1426    ++L1D0cache.demand_misses;
1427  }
1428
1429  action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
1430    ++L1D1cache.demand_misses;
1431  }
1432
1433  action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
1434    ++L1Icache.demand_misses;
1435  }
1436
1437  action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
1438    ++L2cache.demand_misses;
1439  }
1440
1441  action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
1442    probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1443  }
1444
1445  action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
1446    mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1447  }
1448  // END ACTIONS
1449
1450  // BEGIN TRANSITIONS
1451
1452  // transitions from base
1453  transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} {
1454    // track misses, if implemented
1455    // since in I state, L2 miss as well
1456    l2m_profileMiss;
1457    l10m_profileMiss;
1458    a0_allocateL1D;
1459    l1im_profileMiss;
1460    a2_allocateL2;
1461    i1_invCluster;
1462    ii_invIcache;
1463    n_issueRdBlk;
1464    p_popMandatoryQueue;
1465  }
1466
1467  transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} {
1468    // track misses, if implemented
1469    // since in I state, L2 miss as well
1470    l2m_profileMiss;
1471    l11m_profileMiss;
1472    a1_allocateL1D;
1473    a2_allocateL2;
1474    i0_invCluster;
1475    ii_invIcache;
1476    n_issueRdBlk;
1477    p_popMandatoryQueue;
1478  }
1479
1480  transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1481    // track misses, if implemented
1482    // L2 miss as well
1483    l10m_profileMiss;
1484    l2m_profileMiss;
1485    l1im_profileMiss;
1486    ai_allocateL1I;
1487    a2_allocateL2;
1488    ib_invBothClusters;
1489    nS_issueRdBlkS;
1490    p_popMandatoryQueue;
1491  }
1492
1493  transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1494     l11m_profileMiss;
1495    // track misses, if implemented
1496    // L2 miss as well
1497    l2m_profileMiss;
1498    l1im_profileMiss;
1499    ai_allocateL1I;
1500    a2_allocateL2;
1501    ib_invBothClusters;
1502    nS_issueRdBlkS;
1503    p_popMandatoryQueue;
1504  }
1505
1506  transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead,L2TagArrayRead} {
1507    l2m_profileMiss;
1508    l10m_profileMiss;
1509    a0_allocateL1D;
1510    a2_allocateL2;
1511    i1_invCluster;
1512    ii_invIcache;
1513    nM_issueRdBlkM;
1514    p_popMandatoryQueue;
1515  }
1516
1517  transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} {
1518    l2m_profileMiss;
1519    l11m_profileMiss;
1520    a1_allocateL1D;
1521    a2_allocateL2;
1522    i0_invCluster;
1523    ii_invIcache;
1524    nM_issueRdBlkM;
1525    p_popMandatoryQueue;
1526  }
1527
1528  transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1529    l10m_profileMiss;
1530    a0_allocateL1D;
1531    f0_L2ToL1;
1532    p_popMandatoryQueue;
1533  }
1534
1535  transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1536    l11m_profileMiss;
1537    a1_allocateL1D;
1538    f1_L2ToL1;
1539    p_popMandatoryQueue;
1540  }
1541
1542  transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1543    l1im_profileMiss;
1544    ai_allocateL1I;
1545    fi_L2ToL1;
1546    p_popMandatoryQueue;
1547  }
1548
1549  transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1550    l1im_profileMiss;
1551    ai_allocateL1I;
1552    fi_L2ToL1;
1553    p_popMandatoryQueue;
1554  }
1555
1556  transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead}{
1557    l2m_profileMiss;
1558    l10m_profileMiss;
1559    a0_allocateL1D;
1560    i1_invCluster;
1561    ii_invIcache;
1562    nM_issueRdBlkM;
1563    p_popMandatoryQueue;
1564  }
1565
1566  transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead,L2TagArrayRead} {
1567    l2m_profileMiss;
1568    l11m_profileMiss;
1569    a1_allocateL1D;
1570    i0_invCluster;
1571    ii_invIcache;
1572    nM_issueRdBlkM;
1573    p_popMandatoryQueue;
1574  }
1575  transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1576     l10m_profileMiss;
1577    a0_allocateL1D;
1578    f0_L2ToL1;
1579    p_popMandatoryQueue;
1580  }
1581
1582  transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1583     l11m_profileMiss;
1584    a1_allocateL1D;
1585    f1_L2ToL1;
1586    p_popMandatoryQueue;
1587  }
1588
1589  transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1590      l1im_profileMiss;
1591     i2_invL2;
1592    ai_allocateL1I;
1593    a2_allocateL2;
1594    ib_invBothClusters;
1595    nS_issueRdBlkS;
1596    p_popMandatoryQueue;
1597  }
1598
1599  transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1600     l1im_profileMiss;
1601    i2_invL2;
1602    ai_allocateL1I;
1603    a2_allocateL2;
1604    ib_invBothClusters;
1605    nS_issueRdBlkS;
1606    p_popMandatoryQueue;
1607  }
1608
1609  // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW
1610  transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayWrite,L1D0TagArrayRead, L2TagArrayRead, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1611    a0_allocateL1D;
1612    i1_invCluster;
1613    s0_storeDone;   // instantaneous L1/L2 dirty - no writethrough delay
1614    p_popMandatoryQueue;
1615  }
1616
1617  transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1618    a1_allocateL1D;
1619    i0_invCluster;
1620    s1_storeDone;
1621    p_popMandatoryQueue;
1622  }
1623
1624  transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1625     l10m_profileMiss;
1626    a0_allocateL1D;
1627    f0_L2ToL1;
1628    p_popMandatoryQueue;
1629  }
1630
1631  transition(E0, C1_Load_L1miss, E0_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1632     l11m_profileMiss;
1633    a1_allocateL1D;
1634    f1_L2ToL1;
1635    p_popMandatoryQueue;
1636  }
1637
1638  transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1639    l2m_profileMiss; // permissions miss, still issue RdBlkS
1640    l1im_profileMiss;
1641    i2_invL2;
1642    ai_allocateL1I;
1643    a2_allocateL2;
1644    i0_invCluster;
1645    nS_issueRdBlkS;
1646    p_popMandatoryQueue;
1647  }
1648
1649  transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead } {
1650    l2m_profileMiss; // permissions miss, still issue RdBlkS
1651    l1im_profileMiss;
1652    i2_invL2;
1653    ai_allocateL1I;
1654    a2_allocateL2;
1655    i0_invCluster;
1656    nS_issueRdBlkS;
1657    p_popMandatoryQueue;
1658  }
1659
1660  transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1661    a0_allocateL1D;
1662    s0_storeDone;
1663    p_popMandatoryQueue;
1664  }
1665
1666  transition(E0, C1_Store_L1miss, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1667    a1_allocateL1D;
1668    l11m_profileMiss;
1669    i0_invCluster;
1670    s1_storeDone;
1671    p_popMandatoryQueue;
1672  }
1673
1674  transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1675    a1_allocateL1D;
1676    l11m_profileMiss;
1677    f1_L2ToL1;
1678    p_popMandatoryQueue;
1679  }
1680
1681  transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1682    a0_allocateL1D;
1683    l10m_profileMiss;
1684    f0_L2ToL1;
1685    p_popMandatoryQueue;
1686  }
1687
1688  transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} {
1689    l2m_profileMiss; // permissions miss, still issue RdBlkS
1690    l1im_profileMiss;
1691    i2_invL2;
1692    ai_allocateL1I;
1693    a2_allocateL2;
1694    i1_invCluster;
1695    nS_issueRdBlkS;
1696    p_popMandatoryQueue;
1697  }
1698
1699  transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead,L1ITagArrayRead} {
1700    l2m_profileMiss; // permissions miss, still issue RdBlkS
1701    l1im_profileMiss;
1702    i2_invL2;
1703    ai_allocateL1I;
1704    a2_allocateL2;
1705    i1_invCluster;
1706    nS_issueRdBlkS;
1707    p_popMandatoryQueue;
1708  }
1709
1710  transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1711    a1_allocateL1D;
1712    s1_storeDone;
1713    p_popMandatoryQueue;
1714  }
1715
1716  transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1717     l10m_profileMiss;
1718    a0_allocateL1D;
1719    i1_invCluster;
1720    s0_storeDone;
1721    p_popMandatoryQueue;
1722  }
1723
1724  transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1725    l2m_profileMiss; // permissions miss, still issue CtoD
1726     l10m_profileMiss;
1727    a0_allocateL1D;
1728    i1_invCluster;
1729    ii_invIcache;
1730    nM_issueRdBlkM;
1731    p_popMandatoryQueue;
1732  }
1733
1734  transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1735    l2m_profileMiss; // permissions miss, still issue RdBlkS
1736    l11m_profileMiss;
1737    a1_allocateL1D;
1738    i0_invCluster;
1739    ii_invIcache;
1740    nM_issueRdBlkM;
1741    p_popMandatoryQueue;
1742  }
1743
1744  transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1745    l10m_profileMiss;
1746    a0_allocateL1D;
1747    f0_L2ToL1;
1748    p_popMandatoryQueue;
1749  }
1750
1751  transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1752    l11m_profileMiss;
1753    a1_allocateL1D;
1754    f1_L2ToL1;
1755    p_popMandatoryQueue;
1756  }
1757
1758  transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1759    l10m_profileMiss;
1760    a0_allocateL1D;
1761    f0_L2ToL1;
1762    p_popMandatoryQueue;
1763  }
1764
1765  transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1766    l11m_profileMiss;
1767    a1_allocateL1D;
1768    f1_L2ToL1;
1769    p_popMandatoryQueue;
1770  }
1771
1772  transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead,  L2TagArrayRead} {
1773    l2m_profileMiss;  // permissions miss
1774    l1im_profileMiss;
1775    ai_allocateL1I;
1776    t_allocateTBE;
1777    ib_invBothClusters;
1778    vd_victim;
1779//    i2_invL2;
1780    p_popMandatoryQueue;
1781  }
1782
1783  transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead L2TagArrayRead } {
1784    l2m_profileMiss;  // permissions miss
1785    l10m_profileMiss;
1786    ai_allocateL1I;
1787    t_allocateTBE;
1788    ib_invBothClusters;
1789    vd_victim;
1790//    i2_invL2;
1791    p_popMandatoryQueue;
1792  }
1793
1794  transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1795    a0_allocateL1D;
1796    i1_invCluster;
1797    s0_storeDone;
1798    p_popMandatoryQueue;
1799  }
1800
1801  transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1802    a1_allocateL1D;
1803    i0_invCluster;
1804    s1_storeDone;
1805    p_popMandatoryQueue;
1806  }
1807
1808  transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1809   l10m_profileMiss;
1810    a0_allocateL1D;
1811    f0_L2ToL1;
1812    p_popMandatoryQueue;
1813  }
1814
1815  transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D1TagArrayRead} {
1816   l11m_profileMiss;
1817    a1_allocateL1D;
1818    f1_L2ToL1;
1819    p_popMandatoryQueue;
1820  }
1821
1822  transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} {
1823    a0_allocateL1D;
1824    s0_storeDone;
1825    p_popMandatoryQueue;
1826  }
1827
1828  transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1829    a1_allocateL1D;
1830    i0_invCluster;
1831    s1_storeDone;
1832    p_popMandatoryQueue;
1833  }
1834
1835  transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1836    l10m_profileMiss;
1837    a0_allocateL1D;
1838    f0_L2ToL1;
1839    p_popMandatoryQueue;
1840  }
1841
1842  transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead L2TagArrayRead, L2DataArrayRead} {
1843   l11m_profileMiss;
1844    a1_allocateL1D;
1845    f1_L2ToL1;
1846    p_popMandatoryQueue;
1847  }
1848
1849  transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1850    a0_allocateL1D;
1851    i1_invCluster;
1852    s0_storeDone;
1853    p_popMandatoryQueue;
1854  }
1855
1856  transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite} {
1857    a1_allocateL1D;
1858    s1_storeDone;
1859    p_popMandatoryQueue;
1860  }
1861
1862  // end transitions from base
1863
1864  // Begin simple hit transitions
1865  transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es,
1866          Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} {
1867    // track hits, if implemented
1868    l0_loadDone;
1869    p_popMandatoryQueue;
1870  }
1871
1872  transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es,
1873          Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} {
1874    // track hits, if implemented
1875    l1_loadDone;
1876    p_popMandatoryQueue;
1877  }
1878
1879  transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} {
1880    // track hits, if implemented
1881    il0_loadDone;
1882    p_popMandatoryQueue;
1883  }
1884
1885  transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} {
1886    // track hits, if implemented
1887    il1_loadDone;
1888    p_popMandatoryQueue;
1889  }
1890
1891  // end simple hit transitions
1892
1893  // Transitions from transient states
1894
1895  // recycles
1896  transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1897          IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1898          E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} {
1899    zz_recycleMandatoryQueue;
1900  }
1901
1902  transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1,
1903          O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} {
1904    zz_recycleMandatoryQueue;
1905  }
1906
1907  transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1908          IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1909          E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} {
1910    zz_recycleMandatoryQueue;
1911  }
1912
1913  transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0,
1914          O_M0, S0, S1, I_C, S0_C, S1_C, S_C},  C1_Load_L1miss) {} {
1915    zz_recycleMandatoryQueue;
1916  }
1917
1918  transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} {
1919    zz_recycleMandatoryQueue;
1920  }
1921
1922  transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES,
1923          IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F,
1924          O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F,
1925          E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C,
1926          S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} {
1927    zz_recycleMandatoryQueue;
1928  }
1929
1930  transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1,
1931          Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms,
1932          M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} {
1933    zz_recycleMandatoryQueue;
1934  }
1935
1936  transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0,
1937          Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F,
1938          M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} {
1939    zz_recycleMandatoryQueue;
1940  }
1941
1942  transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1943          IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} {
1944    zz_recycleMandatoryQueue;
1945  }
1946
1947  transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1948          IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1,
1949          O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F,
1950          M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} {
1951    zz_recycleMandatoryQueue;
1952  }
1953
1954  transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1955          IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1956          E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} {
1957    zz_recycleMandatoryQueue;
1958  }
1959
1960  transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1961          IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1962          E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} {
1963    zz_recycleMandatoryQueue;
1964  }
1965
1966  transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} {
1967    zz_recycleMandatoryQueue;
1968  }
1969
1970  transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} {
1971    zz_recycleMandatoryQueue;
1972  }
1973
1974  transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS,
1975          PrbInvData, PrbInvDataDemand, PrbInv, PrbShrData, PrbShrDataDemand}) {} {
1976    zz_recycleMandatoryQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1977  }
1978
1979  transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} {
1980    zz_recycleMandatoryQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1981  }
1982
1983  transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} {
1984    l10m_profileMiss;
1985    a0_allocateL1D;
1986    f0_L2ToL1;
1987    p_popMandatoryQueue;
1988  }
1989
1990  transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} {
1991    l10m_profileMiss;
1992    a0_allocateL1D;
1993    f0_L2ToL1;
1994    p_popMandatoryQueue;
1995  }
1996
1997  transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} {
1998    l10m_profileMiss;
1999    a0_allocateL1D;
2000    f0_L2ToL1;
2001    p_popMandatoryQueue;
2002  }
2003
2004  transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} {
2005    l10m_profileMiss;
2006    a0_allocateL1D;
2007    f0_L2ToL1;
2008    p_popMandatoryQueue;
2009  }
2010
2011  transition(I_M0, C1_Load_L1miss, I_M0Ms){
2012    l11m_profileMiss;
2013    l2m_profileMiss;
2014    a1_allocateL1D;
2015    p_popMandatoryQueue;
2016  }
2017
2018  transition(I_M1, C0_Load_L1miss, I_M1Ms){
2019    l10m_profileMiss;
2020    l2m_profileMiss;
2021    a0_allocateL1D;
2022    p_popMandatoryQueue;
2023  }
2024
2025  transition(I_M0, C1_Store_L1miss, I_M0M1) {
2026    l11m_profileMiss;
2027    l2m_profileMiss;
2028    a1_allocateL1D;
2029    p_popMandatoryQueue;
2030  }
2031
2032  transition(I_M1, C0_Store_L1miss, I_M1M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
2033    l2m_profileMiss;
2034    a0_allocateL1D;
2035    p_popMandatoryQueue;
2036  }
2037
2038  transition(I_E0S, C1_Load_L1miss, I_ES) {} {
2039    l2m_profileMiss;
2040    l11m_profileMiss;
2041    a1_allocateL1D;
2042    p_popMandatoryQueue;
2043  }
2044
2045  transition(I_E1S, C0_Load_L1miss, I_ES) {} {
2046    l2m_profileMiss;
2047    l10m_profileMiss;
2048    l2m_profileMiss;
2049    a0_allocateL1D;
2050    p_popMandatoryQueue;
2051  }
2052
2053  transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} {
2054    l11m_profileMiss;
2055    a1_allocateL1D;
2056    f1_L2ToL1;
2057    p_popMandatoryQueue;
2058  }
2059
2060  transition(S_F0, C1_Load_L1miss, S_F) { L2DataArrayRead} {
2061    l11m_profileMiss;
2062    a1_allocateL1D;
2063    f1_L2ToL1;
2064    p_popMandatoryQueue;
2065  }
2066
2067  transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} {
2068    l11m_profileMiss;
2069    a1_allocateL1D;
2070    f1_L2ToL1;
2071    p_popMandatoryQueue;
2072  }
2073
2074  transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) {L2DataArrayRead} {
2075    l11m_profileMiss;
2076    a1_allocateL1D;
2077    f1_L2ToL1;
2078    p_popMandatoryQueue;
2079  }
2080
2081  transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} {
2082    i0_invCluster;
2083  }
2084
2085  transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} {
2086    i1_invCluster;
2087  }
2088
2089  transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} {
2090    ii_invIcache;
2091  }
2092
2093  transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead,L1D0TagArrayRead, L1D1TagArrayRead, L1ITagArrayRead} {
2094    forward_eviction_to_cpu0;
2095    forward_eviction_to_cpu1;
2096    t_allocateTBE;
2097    vc_victim;
2098    ib_invBothClusters;
2099    i2_invL2;
2100    ii_invIcache;
2101  }
2102
2103  transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayRead, L1D1TagArrayRead} {
2104    forward_eviction_to_cpu0;
2105    forward_eviction_to_cpu1;
2106    t_allocateTBE;
2107    vd_victim;
2108    i2_invL2;
2109    ib_invBothClusters;  // nothing will happen for D0 on M1, vice versa
2110  }
2111
2112  transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2113    wi_writeIcache;
2114    xi0_loadDone;
2115    uu_sendUnblock;
2116    sdv_sendDoneValid;
2117    pr_popResponseQueue;
2118  }
2119
2120  transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2121    wi_writeIcache;
2122    xi1_loadDone;
2123    sdv_sendDoneValid;
2124    uu_sendUnblock;
2125    pr_popResponseQueue;
2126  }
2127
2128  transition(S0_C, NB_AckS, S_C) { L1IDataArrayWrite,L2DataArrayWrite} {
2129    // does not need send done since the rdblks was "sinked"
2130    wi_writeIcache;
2131    xi0_loadDone;
2132    uu_sendUnblock;
2133    pr_popResponseQueue;
2134  }
2135
2136  transition(S1_C, NB_AckS, S_C) { L1D1DataArrayWrite,L2DataArrayWrite} {
2137    wi_writeIcache;
2138    xi1_loadDone;
2139    uu_sendUnblock;
2140    pr_popResponseQueue;
2141  }
2142
2143  transition(I_M0, NB_AckM, M0) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2144    w0_writeDcache;
2145    xs0_storeDone;
2146    sdv_sendDoneValid;
2147    uu_sendUnblock;
2148    pr_popResponseQueue;
2149  }
2150
2151  transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2152    w1_writeDcache;
2153    xs1_storeDone;
2154    sdv_sendDoneValid;
2155    uu_sendUnblock;
2156    pr_popResponseQueue;
2157  }
2158
2159  // THESE MO->M1 should not be instantaneous but oh well for now.
2160  transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2161    w0_writeDcache;
2162    xs0_storeDone;
2163    sdv_sendDoneValid;
2164    uu_sendUnblock;
2165    i0_invCluster;
2166    s1_storeDone;
2167    pr_popResponseQueue;
2168  }
2169
2170  transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2171    w1_writeDcache;
2172    xs1_storeDone;
2173    sdv_sendDoneValid;
2174    uu_sendUnblock;
2175    i1_invCluster;
2176    s0_storeDone;
2177    pr_popResponseQueue;
2178  }
2179
2180  // Above shoudl be more like this, which has some latency to xfer to L1
2181  transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} {
2182    w0_writeDcache;
2183    xs0_storeDone;
2184    sdv_sendDoneValid;
2185    uu_sendUnblock;
2186    f1_L2ToL1;
2187    pr_popResponseQueue;
2188  }
2189
2190  transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite,L2DataArrayWrite} {
2191    w1_writeDcache;
2192    xs1_storeDone;
2193    sdv_sendDoneValid;
2194    uu_sendUnblock;
2195    f0_L2ToL1;
2196    pr_popResponseQueue;
2197  }
2198
2199  transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2200    w0_writeDcache;
2201    xl0_loadDone;
2202    sdv_sendDoneValid;
2203    uu_sendUnblock;
2204    pr_popResponseQueue;
2205  }
2206
2207  transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2208    w1_writeDcache;
2209    xl1_loadDone;
2210    sdv_sendDoneValid;
2211    uu_sendUnblock;
2212    pr_popResponseQueue;
2213  }
2214
2215  transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } {
2216    w0_writeDcache;
2217    xl0_loadDone;
2218    w1_writeDcache;
2219    xl1_loadDone;
2220    sdv_sendDoneValid;
2221    uu_sendUnblock;
2222    pr_popResponseQueue;
2223  }
2224
2225  transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2226    w0_writeDcache;
2227    xl0_loadDone;
2228    sdv_sendDoneValid;
2229    uu_sendUnblock;
2230    pr_popResponseQueue;
2231  }
2232
2233  transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2234    w1_writeDcache;
2235    xl1_loadDone;
2236    sdv_sendDoneValid;
2237    uu_sendUnblock;
2238    pr_popResponseQueue;
2239  }
2240
2241  transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite,  L2DataArrayWrite} {
2242    w0_writeDcache;
2243    xl0_loadDone;
2244    w1_writeDcache;
2245    xl1_loadDone;
2246    sdv_sendDoneValid;
2247    uu_sendUnblock;
2248    pr_popResponseQueue;
2249  }
2250
2251  transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2252    c0_copyL2ToL1;
2253    l0_loadDone;
2254    pt_popTriggerQueue;
2255  }
2256
2257  transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2258    c1_copyL2ToL1;
2259    l1_loadDone;
2260    pt_popTriggerQueue;
2261  }
2262
2263  transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2264    ci_copyL2ToL1;
2265    il0_loadDone;
2266    pt_popTriggerQueue;
2267  }
2268
2269  transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2270    ci_copyL2ToL1;
2271    il1_loadDone;
2272    pt_popTriggerQueue;
2273  }
2274
2275  transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2276    c0_copyL2ToL1;
2277    l0_loadDone;
2278    pt_popTriggerQueue;
2279  }
2280
2281  transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2282    c1_copyL2ToL1;
2283    l1_loadDone;
2284    pt_popTriggerQueue;
2285  }
2286
2287  transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2288    c0_copyL2ToL1;
2289    l0_loadDone;
2290    pt_popTriggerQueue;
2291  }
2292
2293  transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2294    c1_copyL2ToL1;
2295    l1_loadDone;
2296    pt_popTriggerQueue;
2297  }
2298
2299  transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2300    c0_copyL2ToL1;
2301    l0_loadDone;
2302    pt_popTriggerQueue;
2303  }
2304
2305  transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2306    c1_copyL2ToL1;
2307    l1_loadDone;
2308    pt_popTriggerQueue;
2309  }
2310
2311  transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2312    c1_copyL2ToL1;
2313    l1_loadDone;
2314    pt_popTriggerQueue;
2315  }
2316
2317  transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2318    c0_copyL2ToL1;
2319    l0_loadDone;
2320    pt_popTriggerQueue;
2321  }
2322
2323  transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2324    c0_copyL2ToL1;
2325    l0_loadDone;
2326    pt_popTriggerQueue;
2327  }
2328
2329  transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2330    c1_copyL2ToL1;
2331    l1_loadDone;
2332    pt_popTriggerQueue;
2333  }
2334
2335  transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} {
2336    c0_copyL2ToL1;
2337    l0_loadDone;
2338    pt_popTriggerQueue;
2339  }
2340
2341  transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} {
2342    c1_copyL2ToL1;
2343    l1_loadDone;
2344    pt_popTriggerQueue;
2345  }
2346
2347  transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2348    c0_copyL2ToL1;
2349    l0_loadDone;
2350    pt_popTriggerQueue;
2351  }
2352
2353  transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2354    c1_copyL2ToL1;
2355    l1_loadDone;
2356    pt_popTriggerQueue;
2357  }
2358
2359  transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2360    c0_copyL2ToL1;
2361    l0_loadDone;
2362    pt_popTriggerQueue;
2363  }
2364
2365  transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2366    c1_copyL2ToL1;
2367    l1_loadDone;
2368    pt_popTriggerQueue;
2369  }
2370
2371  transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} {
2372    c0_copyL2ToL1;
2373    l0_loadDone;
2374    pt_popTriggerQueue;
2375  }
2376
2377  transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} {
2378    c1_copyL2ToL1;
2379    l1_loadDone;
2380    pt_popTriggerQueue;
2381  }
2382
2383  transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} {
2384    c0_copyL2ToL1;
2385    l0_loadDone;
2386    pt_popTriggerQueue;
2387  }
2388
2389  transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} {
2390    c1_copyL2ToL1;
2391    l1_loadDone;
2392    pt_popTriggerQueue;
2393  }
2394
2395  transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} {
2396    c0_copyL2ToL1;
2397    l0_loadDone;
2398    pt_popTriggerQueue;
2399  }
2400
2401  transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} {
2402    c1_copyL2ToL1;
2403    l1_loadDone;
2404    pt_popTriggerQueue;
2405  }
2406
2407  transition(IF_E0S, L2_to_L1D0, I_E0S) {} {
2408    pt_popTriggerQueue;
2409  }
2410
2411  transition(IF_E1S, L2_to_L1D1, I_E1S) {} {
2412    pt_popTriggerQueue;
2413  }
2414
2415  transition(IF_ES, L2_to_L1D0, IF1_ES) {} {
2416    pt_popTriggerQueue;
2417  }
2418
2419  transition(IF_ES, L2_to_L1D1, IF0_ES) {} {
2420    pt_popTriggerQueue;
2421  }
2422
2423  transition(IF0_ES, L2_to_L1D0, I_ES) {} {
2424    pt_popTriggerQueue;
2425  }
2426
2427  transition(IF1_ES, L2_to_L1D1, I_ES) {} {
2428    pt_popTriggerQueue;
2429  }
2430
2431  transition(F_S0, L2_to_L1I, S0) {} {
2432    pt_popTriggerQueue;
2433  }
2434
2435  transition(F_S1, L2_to_L1I, S1) {} {
2436    pt_popTriggerQueue;
2437  }
2438
2439  transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2440    xs0_storeDone;
2441    sdv_sendDoneValid;
2442    uu_sendUnblock;
2443    pr_popResponseQueue;
2444  }
2445
2446  transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2447    xs1_storeDone;
2448    sdv_sendDoneValid;
2449    uu_sendUnblock;
2450    pr_popResponseQueue;
2451  }
2452
2453  transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} {
2454    wb_data;
2455    ra_sendReplAck;
2456    sdi_sendDoneInvalid;
2457    d_deallocateTBE;
2458    pr_popResponseQueue;
2459  }
2460
2461  transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} {
2462    wb_data;
2463    ra_sendReplAck;
2464    sdi_sendDoneInvalid;
2465    d_deallocateTBE;
2466    pr_popResponseQueue;
2467  }
2468
2469  transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} {
2470    wb_data;
2471    i2_invL2;
2472    a2_allocateL2;
2473    sdv_sendDoneValid;
2474    nS_issueRdBlkS;
2475    d_deallocateTBE; // FOO
2476    pr_popResponseQueue;
2477  }
2478
2479  transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} {
2480    wb_data;
2481    i2_invL2;
2482    a2_allocateL2;
2483    sdv_sendDoneValid;
2484    nS_issueRdBlkS;
2485    d_deallocateTBE; // FOO
2486    pr_popResponseQueue;
2487  }
2488
2489  // Writeback cancel "ack"
2490  transition(I_C, NB_AckWB, I) {L2TagArrayWrite} {
2491    ss_sendStaleNotification;
2492    sdi_sendDoneInvalid;
2493    d_deallocateTBE;
2494    pr_popResponseQueue;
2495  }
2496
2497  transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} {
2498    ss_sendStaleNotification;
2499    sdv_sendDoneValid;
2500    pr_popResponseQueue;
2501  }
2502
2503  transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} {
2504    ss_sendStaleNotification;
2505    sdv_sendDoneValid;
2506    pr_popResponseQueue;
2507  }
2508
2509  transition(S_C, NB_AckWB, S) {L2TagArrayWrite} {
2510    ss_sendStaleNotification;
2511    sdv_sendDoneValid;
2512    pr_popResponseQueue;
2513  }
2514
2515  // Begin Probe Transitions
2516
2517  transition({Ms, M0, M1, O}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2518    forward_eviction_to_cpu0;
2519    forward_eviction_to_cpu1;
2520    pd_sendProbeResponseData;
2521    i2_invL2;
2522    ib_invBothClusters;
2523    pp_popProbeQueue;
2524  }
2525
2526  transition({Es, E0, E1, S, I}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite} {
2527    forward_eviction_to_cpu0;
2528    forward_eviction_to_cpu1;
2529    pi_sendProbeResponseInv;
2530    i2_invL2;
2531    ib_invBothClusters;
2532    ii_invIcache;  // only relevant for S
2533    pp_popProbeQueue;
2534  }
2535
2536  transition(S_C, {PrbInvData, PrbInvDataDemand}, I_C) {L2TagArrayWrite} {
2537    t_allocateTBE;
2538    forward_eviction_to_cpu0;
2539    forward_eviction_to_cpu1;
2540    pi_sendProbeResponseInv;
2541    i2_invL2;
2542    ib_invBothClusters;
2543    ii_invIcache;
2544    pp_popProbeQueue;
2545  }
2546
2547  transition(I_C, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2548    pi_sendProbeResponseInv;
2549    ib_invBothClusters;
2550    pp_popProbeQueue;
2551  }
2552
2553  transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} {
2554    forward_eviction_to_cpu0;
2555    forward_eviction_to_cpu1;
2556    pi_sendProbeResponseInv;
2557    i2_invL2; // nothing will happen in I
2558    ib_invBothClusters;
2559    ii_invIcache;
2560    pp_popProbeQueue;
2561  }
2562
2563  transition(S_C, PrbInv, I_C) {L2TagArrayWrite} {
2564    t_allocateTBE;
2565    forward_eviction_to_cpu0;
2566    forward_eviction_to_cpu1;
2567    pi_sendProbeResponseInv;
2568    i2_invL2;
2569    ib_invBothClusters;
2570    ii_invIcache;
2571    pp_popProbeQueue;
2572  }
2573
2574  transition(I_C, PrbInv, I_C) {} {
2575    pi_sendProbeResponseInv;
2576    ib_invBothClusters;
2577    ii_invIcache;
2578    pp_popProbeQueue;
2579  }
2580
2581  transition({Ms, M0, M1, O}, {PrbShrData, PrbShrDataDemand}, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2582    pd_sendProbeResponseData;
2583    pp_popProbeQueue;
2584  }
2585
2586  transition({Es, E0, E1, S}, {PrbShrData, PrbShrDataDemand}, S) {L2TagArrayRead, L2TagArrayWrite} {
2587    ph_sendProbeResponseHit;
2588    pp_popProbeQueue;
2589  }
2590
2591  transition(S_C, {PrbShrData, PrbShrDataDemand}) {} {
2592    ph_sendProbeResponseHit;
2593    pp_popProbeQueue;
2594  }
2595
2596  transition({I, I_C}, {PrbShrData, PrbShrDataDemand}) {L2TagArrayRead} {
2597    pb_sendProbeResponseBackprobe;
2598    pp_popProbeQueue;
2599  }
2600
2601  transition({I_M0, I_E0S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2602    pi_sendProbeResponseInv;
2603    ib_invBothClusters;  // must invalidate current data (only relevant for I_M0)
2604    a0_allocateL1D;  // but make sure there is room for incoming data when it arrives
2605    pp_popProbeQueue;
2606  }
2607
2608  transition({I_M1, I_E1S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2609    pi_sendProbeResponseInv;
2610    ib_invBothClusters; // must invalidate current data (only relevant for I_M1)
2611    a1_allocateL1D;  // but make sure there is room for incoming data when it arrives
2612    pp_popProbeQueue;
2613  }
2614
2615  transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbInvDataDemand, PrbShrData, PrbShrDataDemand}) {} {
2616    pi_sendProbeResponseInv;
2617    ib_invBothClusters;
2618    a0_allocateL1D;
2619    a1_allocateL1D;
2620    pp_popProbeQueue;
2621  }
2622
2623  transition({I_M0, I_E0S, I_M1, I_E1S}, {PrbShrData, PrbShrDataDemand}) {} {
2624    pb_sendProbeResponseBackprobe;
2625    pp_popProbeQueue;
2626  }
2627
2628  transition(ES_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2629    pi_sendProbeResponseInv;
2630    ib_invBothClusters;
2631    ii_invIcache;
2632    pp_popProbeQueue;
2633  }
2634
2635  transition(MO_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2636    pdt_sendProbeResponseDataFromTBE;
2637    ib_invBothClusters;
2638    ii_invIcache;
2639    pp_popProbeQueue;
2640  }
2641
2642  transition(MO_I, PrbInv, I_C) {} {
2643    pi_sendProbeResponseInv;
2644    ib_invBothClusters;
2645    ii_invIcache;
2646    pp_popProbeQueue;
2647  }
2648
2649  transition(ES_I, PrbInv, I_C) {} {
2650    pi_sendProbeResponseInv;
2651    ib_invBothClusters;
2652    ii_invIcache;
2653    pp_popProbeQueue;
2654  }
2655
2656  transition(ES_I, {PrbShrData, PrbShrDataDemand}, ES_I) {} {
2657    ph_sendProbeResponseHit;
2658    s_setSharedFlip;
2659    pp_popProbeQueue;
2660  }
2661
2662  transition(MO_I, {PrbShrData, PrbShrDataDemand}, MO_I) {} {
2663    pdt_sendProbeResponseDataFromTBE;
2664    s_setSharedFlip;
2665    pp_popProbeQueue;
2666  }
2667
2668  transition(MO_S0, {PrbInvData, PrbInvDataDemand}, S0_C) {L2TagArrayWrite} {
2669    forward_eviction_to_cpu0;
2670    forward_eviction_to_cpu1;
2671    pdt_sendProbeResponseDataFromTBE;
2672    i2_invL2;
2673    a2_allocateL2;
2674    nS_issueRdBlkS;
2675    d_deallocateTBE;
2676    pp_popProbeQueue;
2677  }
2678
2679  transition(MO_S1, {PrbInvData, PrbInvDataDemand}, S1_C) {} {
2680    forward_eviction_to_cpu0;
2681    forward_eviction_to_cpu1;
2682    pdt_sendProbeResponseDataFromTBE;
2683    i2_invL2;
2684    a2_allocateL2;
2685    nS_issueRdBlkS;
2686    d_deallocateTBE;
2687    pp_popProbeQueue;
2688  }
2689
2690  transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} {
2691    forward_eviction_to_cpu0;
2692    forward_eviction_to_cpu1;
2693    pi_sendProbeResponseInv;
2694    i2_invL2;
2695    a2_allocateL2;
2696    nS_issueRdBlkS;
2697    d_deallocateTBE;
2698    pp_popProbeQueue;
2699  }
2700
2701  transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} {
2702    forward_eviction_to_cpu0;
2703    forward_eviction_to_cpu1;
2704    pi_sendProbeResponseInv;
2705    i2_invL2;
2706    a2_allocateL2;
2707    nS_issueRdBlkS;
2708    d_deallocateTBE;
2709    pp_popProbeQueue;
2710  }
2711
2712  transition({MO_S0, MO_S1}, {PrbShrData, PrbShrDataDemand}) {} {
2713    pdt_sendProbeResponseDataFromTBE;
2714    s_setSharedFlip;
2715    pp_popProbeQueue;
2716  }
2717
2718  transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E0S) {} {
2719    forward_eviction_to_cpu0;
2720    forward_eviction_to_cpu1;
2721    pi_sendProbeResponseInv;
2722    // invalidate everything you've got
2723    ib_invBothClusters;
2724    ii_invIcache;
2725    i2_invL2;
2726    // but make sure you have room for what you need from the fill
2727    a0_allocateL1D;
2728    a2_allocateL2;
2729    n_issueRdBlk;
2730    pp_popProbeQueue;
2731  }
2732
2733  transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E1S) {} {
2734    forward_eviction_to_cpu0;
2735    forward_eviction_to_cpu1;
2736    pi_sendProbeResponseInv;
2737    // invalidate everything you've got
2738    ib_invBothClusters;
2739    ii_invIcache;
2740    i2_invL2;
2741    // but make sure you have room for what you need from the fill
2742    a1_allocateL1D;
2743    a2_allocateL2;
2744    n_issueRdBlk;
2745    pp_popProbeQueue;
2746  }
2747
2748  transition({S_F, Es_F}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_ES) {} {
2749    forward_eviction_to_cpu0;
2750    forward_eviction_to_cpu1;
2751    pi_sendProbeResponseInv;
2752    // invalidate everything you've got
2753    ib_invBothClusters;
2754    ii_invIcache;
2755    i2_invL2;
2756    // but make sure you have room for what you need from the fill
2757    a0_allocateL1D;
2758    a1_allocateL1D;
2759    a2_allocateL2;
2760    n_issueRdBlk;
2761    pp_popProbeQueue;
2762  }
2763
2764  transition(Si_F0, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S0) {} {
2765    forward_eviction_to_cpu0;
2766    forward_eviction_to_cpu1;
2767    pi_sendProbeResponseInv;
2768    ib_invBothClusters;
2769    ii_invIcache;
2770    i2_invL2;
2771    ai_allocateL1I;
2772    a2_allocateL2;
2773    nS_issueRdBlkS;
2774    pp_popProbeQueue;
2775  }
2776
2777  transition(Si_F1, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S1) {} {
2778    forward_eviction_to_cpu0;
2779    forward_eviction_to_cpu1;
2780    pi_sendProbeResponseInv;
2781    ib_invBothClusters;
2782    ii_invIcache;
2783    i2_invL2;
2784    ai_allocateL1I;
2785    a2_allocateL2;
2786    nS_issueRdBlkS;
2787    pp_popProbeQueue;
2788  }
2789
2790  transition({Es_F0, E0_F, E1_Es}, {PrbShrData, PrbShrDataDemand}, S_F0) {} {
2791    ph_sendProbeResponseHit;
2792    pp_popProbeQueue;
2793  }
2794
2795  transition({Es_F1, E1_F, E0_Es}, {PrbShrData, PrbShrDataDemand}, S_F1) {} {
2796    ph_sendProbeResponseHit;
2797    pp_popProbeQueue;
2798  }
2799
2800  transition(Es_F, {PrbShrData, PrbShrDataDemand}, S_F) {} {
2801    ph_sendProbeResponseHit;
2802    pp_popProbeQueue;
2803  }
2804
2805  transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, {PrbShrData, PrbShrDataDemand}) {} {
2806    ph_sendProbeResponseHit;
2807    pp_popProbeQueue;
2808  }
2809
2810  transition(S_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {} {
2811    forward_eviction_to_cpu0;
2812    forward_eviction_to_cpu1;
2813    pim_sendProbeResponseInvMs;
2814    ib_invBothClusters;
2815    ii_invIcache;
2816    i2_invL2;
2817    a0_allocateL1D;
2818    a2_allocateL2;
2819    pp_popProbeQueue;
2820  }
2821
2822  transition(O_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {L2DataArrayRead} {
2823    forward_eviction_to_cpu0;
2824    forward_eviction_to_cpu1;
2825    pdm_sendProbeResponseDataMs;
2826    ib_invBothClusters;
2827    ii_invIcache;
2828    i2_invL2;
2829    a0_allocateL1D;
2830    a2_allocateL2;
2831    pp_popProbeQueue;
2832  }
2833
2834  transition({S_M0, O_M0}, {PrbInv}, I_M0) {} {
2835    forward_eviction_to_cpu0;
2836    forward_eviction_to_cpu1;
2837    pim_sendProbeResponseInvMs;
2838    ib_invBothClusters;
2839    ii_invIcache;
2840    i2_invL2;
2841    a0_allocateL1D;
2842    a2_allocateL2;
2843    pp_popProbeQueue;
2844  }
2845
2846  transition(S_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2847    forward_eviction_to_cpu0;
2848    forward_eviction_to_cpu1;
2849    pim_sendProbeResponseInvMs;
2850    ib_invBothClusters;
2851    ii_invIcache;
2852    i2_invL2;
2853    a1_allocateL1D;
2854    a2_allocateL2;
2855    pp_popProbeQueue;
2856  }
2857
2858  transition(O_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2859    forward_eviction_to_cpu0;
2860    forward_eviction_to_cpu1;
2861    pdm_sendProbeResponseDataMs;
2862    ib_invBothClusters;
2863    ii_invIcache;
2864    i2_invL2;
2865    a1_allocateL1D;
2866    a2_allocateL2;
2867    pp_popProbeQueue;
2868  }
2869
2870  transition({S_M1, O_M1}, {PrbInv}, I_M1) {} {
2871    forward_eviction_to_cpu0;
2872    forward_eviction_to_cpu1;
2873    pim_sendProbeResponseInvMs;
2874    ib_invBothClusters;
2875    ii_invIcache;
2876    i2_invL2;
2877    a1_allocateL1D;
2878    a2_allocateL2;
2879    pp_popProbeQueue;
2880  }
2881
2882  transition({S0, S0_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2883    forward_eviction_to_cpu0;
2884    forward_eviction_to_cpu1;
2885    pi_sendProbeResponseInv;
2886    ib_invBothClusters;
2887    ii_invIcache;
2888    i2_invL2;
2889    ai_allocateL1I;
2890    a2_allocateL2;
2891    pp_popProbeQueue;
2892  }
2893
2894  transition({S1, S1_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2895    forward_eviction_to_cpu0;
2896    forward_eviction_to_cpu1;
2897    pi_sendProbeResponseInv;
2898    ib_invBothClusters;
2899    ii_invIcache;
2900    i2_invL2;
2901    ai_allocateL1I;
2902    a2_allocateL2;
2903    pp_popProbeQueue;
2904  }
2905
2906  transition({S_M0, S_M1}, {PrbShrData, PrbShrDataDemand}) {} {
2907    ph_sendProbeResponseHit;
2908    pp_popProbeQueue;
2909  }
2910
2911  transition({O_M0, O_M1}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
2912    pd_sendProbeResponseData;
2913    pp_popProbeQueue;
2914  }
2915
2916  transition({S0, S1, S0_C, S1_C}, {PrbShrData, PrbShrDataDemand}) {} {
2917    pb_sendProbeResponseBackprobe;
2918    pp_popProbeQueue;
2919  }
2920
2921  transition({Ms_F0, M0_F, M1_Ms, O_F0}, {PrbInvData, PrbInvDataDemand}, IF_E0S) {L2DataArrayRead} {
2922    forward_eviction_to_cpu0;
2923    forward_eviction_to_cpu1;
2924    pd_sendProbeResponseData;
2925    ib_invBothClusters;
2926    i2_invL2;
2927    a0_allocateL1D;
2928    a2_allocateL2;
2929    n_issueRdBlk;
2930    pp_popProbeQueue;
2931  }
2932
2933  transition({Ms_F1, M1_F, M0_Ms, O_F1}, {PrbInvData, PrbInvDataDemand}, IF_E1S) {L2DataArrayRead} {
2934    forward_eviction_to_cpu0;
2935    forward_eviction_to_cpu1;
2936    pd_sendProbeResponseData;
2937    ib_invBothClusters;
2938    i2_invL2;
2939    a1_allocateL1D;
2940    a2_allocateL2;
2941    n_issueRdBlk;
2942    pp_popProbeQueue;
2943  }
2944
2945  transition({Ms_F, O_F}, {PrbInvData, PrbInvDataDemand}, IF_ES) {L2DataArrayRead} {
2946    forward_eviction_to_cpu0;
2947    forward_eviction_to_cpu1;
2948    pd_sendProbeResponseData;
2949    ib_invBothClusters;
2950    i2_invL2;
2951    a0_allocateL1D;
2952    a1_allocateL1D;
2953    a2_allocateL2;
2954    n_issueRdBlk;
2955    pp_popProbeQueue;
2956  }
2957
2958  transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} {
2959    forward_eviction_to_cpu0;
2960    forward_eviction_to_cpu1;
2961    pi_sendProbeResponseInv;
2962    ib_invBothClusters;
2963    i2_invL2;
2964    a0_allocateL1D;
2965    a2_allocateL2;
2966    n_issueRdBlk;
2967    pp_popProbeQueue;
2968  }
2969
2970  transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} {
2971    forward_eviction_to_cpu0;
2972    forward_eviction_to_cpu1;
2973    pi_sendProbeResponseInv;
2974    ib_invBothClusters;
2975    i2_invL2;
2976    a1_allocateL1D;
2977    a2_allocateL2;
2978    n_issueRdBlk;
2979    pp_popProbeQueue;
2980  }
2981
2982  transition({Ms_F, O_F}, PrbInv, IF_ES) {} {
2983    forward_eviction_to_cpu0;
2984    forward_eviction_to_cpu1;
2985    pi_sendProbeResponseInv;
2986    ib_invBothClusters;
2987    i2_invL2;
2988    a0_allocateL1D;
2989    a1_allocateL1D;
2990    a2_allocateL2;
2991    n_issueRdBlk;
2992    pp_popProbeQueue;
2993  }
2994
2995  transition({Ms_F0, M0_F, M1_Ms}, {PrbShrData, PrbShrDataDemand}, O_F0) {L2DataArrayRead} {
2996    pd_sendProbeResponseData;
2997    pp_popProbeQueue;
2998  }
2999
3000  transition({Ms_F1, M1_F, M0_Ms}, {PrbShrData, PrbShrDataDemand}, O_F1) {} {
3001  }
3002
3003  transition({Ms_F}, {PrbShrData, PrbShrDataDemand}, O_F) {L2DataArrayRead} {
3004    pd_sendProbeResponseData;
3005    pp_popProbeQueue;
3006  }
3007
3008  transition({O_F0, O_F1, O_F}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
3009    pd_sendProbeResponseData;
3010    pp_popProbeQueue;
3011  }
3012
3013  // END TRANSITIONS
3014}
3015
3016
3017