1
2/*
3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30
31// CoherenceRequestType
32enumeration(CoherenceRequestType, desc="...") {
33  GETX,      desc="Get eXclusive";
34  UPGRADE,   desc="UPGRADE to exclusive";
35  GETS,      desc="Get Shared";
36  GET_INSTR, desc="Get Instruction";
37  INV,       desc="INValidate";
38  PUTX,      desc="Replacement message";
39
40  WB_ACK,    desc="Writeback ack";
41
42  DMA_READ, desc="DMA Read";
43  DMA_WRITE, desc="DMA Write";
44}
45
46// CoherenceResponseType
47enumeration(CoherenceResponseType, desc="...") {
48  MEMORY_ACK, desc="Ack from memory controller";
49  DATA, desc="Data block for L1 cache in S state";
50  DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
51  MEMORY_DATA, desc="Data block from / to main memory";
52  ACK, desc="Generic invalidate ack";
53  WB_ACK, desc="writeback ack";
54  UNBLOCK, desc="unblock";
55  EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
56  INV, desc="Invalidate from directory";
57}
58
59// RequestMsg
60structure(RequestMsg, desc="...", interface="Message") {
61  Addr addr,              desc="Physical address for this request";
62  CoherenceRequestType Type,    desc="Type of request (GetS, GetX, PutX, etc)";
63  RubyAccessMode AccessMode,    desc="user/supervisor access type";
64  MachineID Requestor      ,    desc="What component request";
65  NetDest Destination,          desc="What components receive the request, includes MachineType and num";
66  MessageSizeType MessageSize,  desc="size category of the message";
67  DataBlock DataBlk,            desc="Data for the cache line (if PUTX)";
68  int Len;
69  bool Dirty, default="false",  desc="Dirty bit";
70  PrefetchBit Prefetch,         desc="Is this a prefetch request";
71
72  bool functionalRead(Packet *pkt) {
73    // Only PUTX messages contains the data block
74    if (Type == CoherenceRequestType:PUTX) {
75        return testAndRead(addr, DataBlk, pkt);
76    }
77
78    return false;
79  }
80
81  bool functionalWrite(Packet *pkt) {
82    // No check on message type required since the protocol should
83    // read data from those messages that contain the block
84    return testAndWrite(addr, DataBlk, pkt);
85  }
86}
87
88// ResponseMsg
89structure(ResponseMsg, desc="...", interface="Message") {
90  Addr addr,              desc="Physical address for this request";
91  CoherenceResponseType Type,   desc="Type of response (Ack, Data, etc)";
92  MachineID Sender,             desc="What component sent the data";
93  NetDest Destination,          desc="Node to whom the data is sent";
94  DataBlock DataBlk,            desc="Data for the cache line";
95  bool Dirty, default="false",  desc="Dirty bit";
96  int AckCount, default="0",  desc="number of acks in this message";
97  MessageSizeType MessageSize,  desc="size category of the message";
98
99  bool functionalRead(Packet *pkt) {
100    // Valid data block is only present in message with following types
101    if (Type == CoherenceResponseType:DATA ||
102        Type == CoherenceResponseType:DATA_EXCLUSIVE ||
103        Type == CoherenceResponseType:MEMORY_DATA) {
104
105        return testAndRead(addr, DataBlk, pkt);
106    }
107
108    return false;
109  }
110
111  bool functionalWrite(Packet *pkt) {
112    // No check on message type required since the protocol should
113    // read data from those messages that contain the block
114    return testAndWrite(addr, DataBlk, pkt);
115  }
116}
117