Network.hh revision 9863:9483739f83ee 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Network class is the base class for classes that implement the
31 * interconnection network between components (processor/cache
32 * components and memory/directory components).  The interconnection
33 * network as described here is not a physical network, but a
34 * programming concept used to implement all communication between
35 * components.  Thus parts of this 'network' will model the on-chip
36 * connections between cache controllers and directory controllers as
37 * well as the links between chip and network switches.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__
41#define __MEM_RUBY_NETWORK_NETWORK_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/protocol/MessageSizeType.hh"
49#include "mem/ruby/common/TypeDefines.hh"
50#include "mem/ruby/network/Topology.hh"
51#include "mem/packet.hh"
52#include "params/RubyNetwork.hh"
53#include "sim/clocked_object.hh"
54
55class NetDest;
56class MessageBuffer;
57class Throttle;
58
59class Network : public ClockedObject
60{
61  public:
62    typedef RubyNetworkParams Params;
63    Network(const Params *p);
64    virtual ~Network() {}
65    const Params * params() const
66    { return dynamic_cast<const Params *>(_params);}
67
68    virtual void init();
69
70    static uint32_t getNumberOfVirtualNetworks() { return m_virtual_networks; }
71    static uint32_t MessageSizeType_to_int(MessageSizeType size_type);
72
73    // returns the queue requested for the given component
74    virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered,
75        int netNumber, std::string vnet_type) = 0;
76    virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered,
77        int netNumber, std::string vnet_type) = 0;
78    virtual const std::vector<Throttle*>* getThrottles(NodeID id) const;
79    virtual int getNumNodes() {return 1;}
80
81    virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
82                             LinkDirection direction,
83                             const NetDest& routing_table_entry) = 0;
84    virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link,
85                            LinkDirection direction,
86                            const NetDest& routing_table_entry) = 0;
87    virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
88                                  LinkDirection direction,
89                                  const NetDest& routing_table_entry) = 0;
90
91    virtual void collateStats() = 0;
92    virtual void print(std::ostream& out) const = 0;
93
94    /*
95     * Virtual functions for functionally reading and writing packets in
96     * the network. Each network needs to implement these for functional
97     * accesses to work correctly.
98     */
99    virtual bool functionalRead(Packet *pkt)
100    { fatal("Functional read not implemented.\n"); }
101    virtual uint32_t functionalWrite(Packet *pkt)
102    { fatal("Functional write not implemented.\n"); }
103
104  protected:
105    // Private copy constructor and assignment operator
106    Network(const Network& obj);
107    Network& operator=(const Network& obj);
108
109    uint32_t m_nodes;
110    static uint32_t m_virtual_networks;
111    Topology* m_topology_ptr;
112    static uint32_t m_control_msg_size;
113    static uint32_t m_data_msg_size;
114
115  private:
116    //! Callback class used for collating statistics from all the
117    //! controller of this type.
118    class StatsCallback : public Callback
119    {
120      private:
121        Network *ctr;
122
123      public:
124        virtual ~StatsCallback() {}
125
126        StatsCallback(Network *_ctr)
127            : ctr(_ctr)
128        {
129        }
130
131        void process() {ctr->collateStats();}
132    };
133};
134
135inline std::ostream&
136operator<<(std::ostream& out, const Network& obj)
137{
138    obj.print(out);
139    out << std::flush;
140    return out;
141}
142
143#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
144