request.hh revision 5731
12381SN/A/* 22381SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32381SN/A * All rights reserved. 42381SN/A * 52381SN/A * Redistribution and use in source and binary forms, with or without 62381SN/A * modification, are permitted provided that the following conditions are 72381SN/A * met: redistributions of source code must retain the above copyright 82381SN/A * notice, this list of conditions and the following disclaimer; 92381SN/A * redistributions in binary form must reproduce the above copyright 102381SN/A * notice, this list of conditions and the following disclaimer in the 112381SN/A * documentation and/or other materials provided with the distribution; 122381SN/A * neither the name of the copyright holders nor the names of its 132381SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Ali Saidi 312381SN/A */ 322381SN/A 332381SN/A/** 342982Sstever@eecs.umich.edu * @file 352982Sstever@eecs.umich.edu * Declaration of a request, the overall memory request consisting of 362381SN/A the parts of the request that are persistent throughout the transaction. 372381SN/A */ 382381SN/A 392381SN/A#ifndef __MEM_REQUEST_HH__ 402381SN/A#define __MEM_REQUEST_HH__ 412381SN/A 424610Ssaidi@eecs.umich.edu#include "base/fast_alloc.hh" 432980Sgblack@eecs.umich.edu#include "sim/host.hh" 444167Sbinkertn@umich.edu#include "sim/core.hh" 452394SN/A 462989Ssaidi@eecs.umich.edu#include <cassert> 472989Ssaidi@eecs.umich.edu 482394SN/Aclass Request; 492394SN/A 502394SN/Atypedef Request* RequestPtr; 512394SN/A 522812Srdreslin@umich.edu 533806Ssaidi@eecs.umich.edu/** ASI information for this request if it exsits. */ 543806Ssaidi@eecs.umich.educonst uint32_t ASI_BITS = 0x000FF; 552395SN/A/** The request is a Load locked/store conditional. */ 565543Ssaidi@eecs.umich.educonst uint32_t LOCKED = 0x00100; 572395SN/A/** The virtual address is also the physical address. */ 585543Ssaidi@eecs.umich.educonst uint32_t PHYSICAL = 0x00200; 592395SN/A/** The request is an ALPHA VPTE pal access (hw_ld). */ 605543Ssaidi@eecs.umich.educonst uint32_t VPTE = 0x00400; 612395SN/A/** Use the alternate mode bits in ALPHA. */ 625543Ssaidi@eecs.umich.educonst uint32_t ALTMODE = 0x00800; 632395SN/A/** The request is to an uncacheable address. */ 645543Ssaidi@eecs.umich.educonst uint32_t UNCACHEABLE = 0x01000; 652395SN/A/** The request should not cause a page fault. */ 663806Ssaidi@eecs.umich.educonst uint32_t NO_FAULT = 0x02000; 672397SN/A/** The request should be prefetched into the exclusive state. */ 685543Ssaidi@eecs.umich.educonst uint32_t PF_EXCLUSIVE = 0x10000; 692397SN/A/** The request should be marked as LRU. */ 705543Ssaidi@eecs.umich.educonst uint32_t EVICT_NEXT = 0x20000; 712495SN/A/** The request should ignore unaligned access faults */ 723806Ssaidi@eecs.umich.educonst uint32_t NO_ALIGN_FAULT = 0x40000; 732814Srdreslin@umich.edu/** The request was an instruction read. */ 743806Ssaidi@eecs.umich.educonst uint32_t INST_READ = 0x80000; 754040Ssaidi@eecs.umich.edu/** This request is for a memory swap. */ 764040Ssaidi@eecs.umich.educonst uint32_t MEM_SWAP = 0x100000; 774040Ssaidi@eecs.umich.educonst uint32_t MEM_SWAP_COND = 0x200000; 785222Sksewell@umich.edu/** The request should ignore unaligned access faults */ 795222Sksewell@umich.educonst uint32_t NO_HALF_WORD_ALIGN_FAULT = 0x400000; 804040Ssaidi@eecs.umich.edu 812395SN/A 824610Ssaidi@eecs.umich.educlass Request : public FastAlloc 832381SN/A{ 842663Sstever@eecs.umich.edu private: 852663Sstever@eecs.umich.edu /** 862663Sstever@eecs.umich.edu * The physical address of the request. Valid only if validPaddr 872663Sstever@eecs.umich.edu * is set. */ 882663Sstever@eecs.umich.edu Addr paddr; 892532SN/A 902663Sstever@eecs.umich.edu /** 912663Sstever@eecs.umich.edu * The size of the request. This field must be set when vaddr or 922663Sstever@eecs.umich.edu * paddr is written via setVirt() or setPhys(), so it is always 932663Sstever@eecs.umich.edu * valid as long as one of the address fields is valid. */ 942381SN/A int size; 952395SN/A 962532SN/A /** Flag structure for the request. */ 972395SN/A uint32_t flags; 982384SN/A 992663Sstever@eecs.umich.edu /** 1002663Sstever@eecs.umich.edu * The time this request was started. Used to calculate 1012663Sstever@eecs.umich.edu * latencies. This field is set to curTick any time paddr or vaddr 1022663Sstever@eecs.umich.edu * is written. */ 1032663Sstever@eecs.umich.edu Tick time; 1042384SN/A 1052384SN/A /** The address space ID. */ 1062384SN/A int asid; 1073806Ssaidi@eecs.umich.edu 1083804Ssaidi@eecs.umich.edu /** This request is to a memory mapped register. */ 1093806Ssaidi@eecs.umich.edu bool mmapedIpr; 1103804Ssaidi@eecs.umich.edu 1112663Sstever@eecs.umich.edu /** The virtual address of the request. */ 1122663Sstever@eecs.umich.edu Addr vaddr; 1132384SN/A 1144040Ssaidi@eecs.umich.edu /** Extra data for the request, such as the return value of 1154040Ssaidi@eecs.umich.edu * store conditional or the compare value for a CAS. */ 1164040Ssaidi@eecs.umich.edu uint64_t extraData; 1172384SN/A 1185714Shsul@eecs.umich.edu /** The context ID (for statistics, typically). */ 1195714Shsul@eecs.umich.edu int _contextId; 1205714Shsul@eecs.umich.edu /** The thread ID (id within this CPU) */ 1215714Shsul@eecs.umich.edu int _threadId; 1222384SN/A 1232381SN/A /** program counter of initiating access; for tracing/debugging */ 1242381SN/A Addr pc; 1252663Sstever@eecs.umich.edu 1262663Sstever@eecs.umich.edu /** Whether or not paddr is valid (has been written yet). */ 1272663Sstever@eecs.umich.edu bool validPaddr; 1282663Sstever@eecs.umich.edu /** Whether or not the asid & vaddr are valid. */ 1292663Sstever@eecs.umich.edu bool validAsidVaddr; 1302663Sstever@eecs.umich.edu /** Whether or not the sc result is valid. */ 1314040Ssaidi@eecs.umich.edu bool validExData; 1325714Shsul@eecs.umich.edu /** Whether or not the context ID is valid. */ 1335714Shsul@eecs.umich.edu bool validContextAndThreadIds; 1342663Sstever@eecs.umich.edu /** Whether or not the pc is valid. */ 1352532SN/A bool validPC; 1362532SN/A 1372532SN/A public: 1382663Sstever@eecs.umich.edu /** Minimal constructor. No fields are initialized. */ 1392663Sstever@eecs.umich.edu Request() 1402663Sstever@eecs.umich.edu : validPaddr(false), validAsidVaddr(false), 1415714Shsul@eecs.umich.edu validExData(false), validContextAndThreadIds(false), validPC(false) 1422663Sstever@eecs.umich.edu {} 1432532SN/A 1442663Sstever@eecs.umich.edu /** 1452663Sstever@eecs.umich.edu * Constructor for physical (e.g. device) requests. Initializes 1462663Sstever@eecs.umich.edu * just physical address, size, flags, and timestamp (to curTick). 1472663Sstever@eecs.umich.edu * These fields are adequate to perform a request. */ 1482663Sstever@eecs.umich.edu Request(Addr _paddr, int _size, int _flags) 1495714Shsul@eecs.umich.edu : validContextAndThreadIds(false) 1502663Sstever@eecs.umich.edu { setPhys(_paddr, _size, _flags); } 1512532SN/A 1522669Sktlim@umich.edu Request(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc, 1535714Shsul@eecs.umich.edu int _context_id, int _thread_id) 1542669Sktlim@umich.edu { 1555714Shsul@eecs.umich.edu setThreadContext(_context_id, _thread_id); 1562669Sktlim@umich.edu setVirt(_asid, _vaddr, _size, _flags, _pc); 1572669Sktlim@umich.edu } 1582669Sktlim@umich.edu 1594610Ssaidi@eecs.umich.edu ~Request() {} // for FastAlloc 1604610Ssaidi@eecs.umich.edu 1612663Sstever@eecs.umich.edu /** 1622663Sstever@eecs.umich.edu * Set up CPU and thread numbers. */ 1635714Shsul@eecs.umich.edu void setThreadContext(int _context_id, int _thread_id) 1642663Sstever@eecs.umich.edu { 1655714Shsul@eecs.umich.edu _contextId = _context_id; 1665714Shsul@eecs.umich.edu _threadId = _thread_id; 1675714Shsul@eecs.umich.edu validContextAndThreadIds = true; 1682663Sstever@eecs.umich.edu } 1692532SN/A 1702663Sstever@eecs.umich.edu /** 1712663Sstever@eecs.umich.edu * Set up a physical (e.g. device) request in a previously 1722663Sstever@eecs.umich.edu * allocated Request object. */ 1732663Sstever@eecs.umich.edu void setPhys(Addr _paddr, int _size, int _flags) 1742663Sstever@eecs.umich.edu { 1755731SSteve.Reinhardt@amd.com assert(_size >= 0); 1762663Sstever@eecs.umich.edu paddr = _paddr; 1772663Sstever@eecs.umich.edu size = _size; 1782663Sstever@eecs.umich.edu flags = _flags; 1792663Sstever@eecs.umich.edu time = curTick; 1802663Sstever@eecs.umich.edu validPaddr = true; 1812663Sstever@eecs.umich.edu validAsidVaddr = false; 1822663Sstever@eecs.umich.edu validPC = false; 1834040Ssaidi@eecs.umich.edu validExData = false; 1843806Ssaidi@eecs.umich.edu mmapedIpr = false; 1852663Sstever@eecs.umich.edu } 1862532SN/A 1872663Sstever@eecs.umich.edu /** 1882663Sstever@eecs.umich.edu * Set up a virtual (e.g., CPU) request in a previously 1892663Sstever@eecs.umich.edu * allocated Request object. */ 1902663Sstever@eecs.umich.edu void setVirt(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc) 1912663Sstever@eecs.umich.edu { 1925731SSteve.Reinhardt@amd.com assert(_size >= 0); 1932663Sstever@eecs.umich.edu asid = _asid; 1942663Sstever@eecs.umich.edu vaddr = _vaddr; 1952663Sstever@eecs.umich.edu size = _size; 1962663Sstever@eecs.umich.edu flags = _flags; 1972663Sstever@eecs.umich.edu pc = _pc; 1982663Sstever@eecs.umich.edu time = curTick; 1992663Sstever@eecs.umich.edu validPaddr = false; 2002663Sstever@eecs.umich.edu validAsidVaddr = true; 2012663Sstever@eecs.umich.edu validPC = true; 2024040Ssaidi@eecs.umich.edu validExData = false; 2033806Ssaidi@eecs.umich.edu mmapedIpr = false; 2042663Sstever@eecs.umich.edu } 2052532SN/A 2062663Sstever@eecs.umich.edu /** Set just the physical address. This should only be used to 2072663Sstever@eecs.umich.edu * record the result of a translation, and thus the vaddr must be 2082663Sstever@eecs.umich.edu * valid before this method is called. Otherwise, use setPhys() 2092663Sstever@eecs.umich.edu * to guarantee that the size and flags are also set. 2102663Sstever@eecs.umich.edu */ 2112663Sstever@eecs.umich.edu void setPaddr(Addr _paddr) 2122663Sstever@eecs.umich.edu { 2132663Sstever@eecs.umich.edu assert(validAsidVaddr); 2142663Sstever@eecs.umich.edu paddr = _paddr; 2152663Sstever@eecs.umich.edu validPaddr = true; 2162663Sstever@eecs.umich.edu } 2172532SN/A 2182663Sstever@eecs.umich.edu /** Accessor for paddr. */ 2192663Sstever@eecs.umich.edu Addr getPaddr() { assert(validPaddr); return paddr; } 2202663Sstever@eecs.umich.edu 2212663Sstever@eecs.umich.edu /** Accessor for size. */ 2222663Sstever@eecs.umich.edu int getSize() { assert(validPaddr || validAsidVaddr); return size; } 2232663Sstever@eecs.umich.edu /** Accessor for time. */ 2242663Sstever@eecs.umich.edu Tick getTime() { assert(validPaddr || validAsidVaddr); return time; } 2255466Snate@binkert.org void resetTime() { assert(validPaddr || validAsidVaddr); time = curTick; } 2265607Snate@binkert.org void 2275607Snate@binkert.org setTime(Tick when) 2285607Snate@binkert.org { 2295607Snate@binkert.org assert(validPaddr || validAsidVaddr); 2305607Snate@binkert.org time = when; 2315607Snate@binkert.org } 2322663Sstever@eecs.umich.edu 2332663Sstever@eecs.umich.edu /** Accessor for flags. */ 2342663Sstever@eecs.umich.edu uint32_t getFlags() { assert(validPaddr || validAsidVaddr); return flags; } 2352663Sstever@eecs.umich.edu /** Accessor for paddr. */ 2362663Sstever@eecs.umich.edu void setFlags(uint32_t _flags) 2372663Sstever@eecs.umich.edu { assert(validPaddr || validAsidVaddr); flags = _flags; } 2382663Sstever@eecs.umich.edu 2392663Sstever@eecs.umich.edu /** Accessor function for vaddr.*/ 2402663Sstever@eecs.umich.edu Addr getVaddr() { assert(validAsidVaddr); return vaddr; } 2412663Sstever@eecs.umich.edu 2422663Sstever@eecs.umich.edu /** Accessor function for asid.*/ 2432663Sstever@eecs.umich.edu int getAsid() { assert(validAsidVaddr); return asid; } 2442663Sstever@eecs.umich.edu 2453804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2463806Ssaidi@eecs.umich.edu uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; } 2473804Ssaidi@eecs.umich.edu 2483804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2493806Ssaidi@eecs.umich.edu void setAsi(uint8_t a) 2503806Ssaidi@eecs.umich.edu { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; } 2513806Ssaidi@eecs.umich.edu 2523804Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2533806Ssaidi@eecs.umich.edu bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; } 2543806Ssaidi@eecs.umich.edu 2553806Ssaidi@eecs.umich.edu /** Accessor function for asi.*/ 2563823Ssaidi@eecs.umich.edu void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; } 2573804Ssaidi@eecs.umich.edu 2582679Sktlim@umich.edu /** Accessor function to check if sc result is valid. */ 2594040Ssaidi@eecs.umich.edu bool extraDataValid() { return validExData; } 2602663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 2614040Ssaidi@eecs.umich.edu uint64_t getExtraData() { assert(validExData); return extraData; } 2622663Sstever@eecs.umich.edu /** Accessor function for store conditional return value.*/ 2634040Ssaidi@eecs.umich.edu void setExtraData(uint64_t _extraData) 2644040Ssaidi@eecs.umich.edu { extraData = _extraData; validExData = true; } 2652663Sstever@eecs.umich.edu 2665714Shsul@eecs.umich.edu /** Accessor function for context ID.*/ 2675714Shsul@eecs.umich.edu int contextId() { assert(validContextAndThreadIds); return _contextId; } 2685714Shsul@eecs.umich.edu /** Accessor function for thread ID. */ 2695714Shsul@eecs.umich.edu int threadId() { assert(validContextAndThreadIds); return _threadId; } 2702663Sstever@eecs.umich.edu 2712663Sstever@eecs.umich.edu /** Accessor function for pc.*/ 2722663Sstever@eecs.umich.edu Addr getPC() { assert(validPC); return pc; } 2732532SN/A 2742811Srdreslin@umich.edu /** Accessor Function to Check Cacheability. */ 2753170Sstever@eecs.umich.edu bool isUncacheable() { return (getFlags() & UNCACHEABLE) != 0; } 2762811Srdreslin@umich.edu 2773170Sstever@eecs.umich.edu bool isInstRead() { return (getFlags() & INST_READ) != 0; } 2783170Sstever@eecs.umich.edu 2793170Sstever@eecs.umich.edu bool isLocked() { return (getFlags() & LOCKED) != 0; } 2802814Srdreslin@umich.edu 2814040Ssaidi@eecs.umich.edu bool isSwap() { return (getFlags() & MEM_SWAP || 2824040Ssaidi@eecs.umich.edu getFlags() & MEM_SWAP_COND); } 2834040Ssaidi@eecs.umich.edu 2844040Ssaidi@eecs.umich.edu bool isCondSwap() { return (getFlags() & MEM_SWAP_COND) != 0; } 2854040Ssaidi@eecs.umich.edu 2865222Sksewell@umich.edu bool inline isMisaligned() {return (!(getFlags() & NO_ALIGN_FAULT) && 2875222Sksewell@umich.edu ((vaddr & 1) || 2885222Sksewell@umich.edu (!(getFlags() & NO_HALF_WORD_ALIGN_FAULT) 2895222Sksewell@umich.edu && (vaddr & 0x2))));} 2904040Ssaidi@eecs.umich.edu 2912641Sstever@eecs.umich.edu friend class Packet; 2922384SN/A}; 2932381SN/A 2942381SN/A#endif // __MEM_REQUEST_HH__ 295