request.hh revision 2495
11689SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39919Ssteve.reinhardt@amd.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 148707Sandreas.hansson@arm.com * this software without specific prior written permission. 151689SN/A * 167897Shestness@cs.utexas.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291689SN/A/** 301689SN/A * @file Decleration of a request, the overall memory request consisting of 311689SN/A the parts of the request that are persistent throughout the transaction. 321689SN/A */ 331689SN/A 341689SN/A#ifndef __MEM_REQUEST_HH__ 351689SN/A#define __MEM_REQUEST_HH__ 361689SN/A 371689SN/A#include "arch/isa_traits.hh" 381689SN/A 391689SN/Aclass Request; 401689SN/Aclass CpuRequest; 412665Ssaidi@eecs.umich.edu 422665Ssaidi@eecs.umich.edutypedef Request* RequestPtr; 432756Sksewell@umich.edutypedef CpuRequest* CpuRequestPtr; 447897Shestness@cs.utexas.edu 451689SN/A/** The request is a Load locked/store conditional. */ 461689SN/Aconst unsigned LOCKED = 0x001; 472325SN/A/** The virtual address is also the physical address. */ 482325SN/Aconst unsigned PHYSICAL = 0x002; 491060SN/A/** The request is an ALPHA VPTE pal access (hw_ld). */ 501060SN/Aconst unsigned VPTE = 0x004; 511060SN/A/** Use the alternate mode bits in ALPHA. */ 522292SN/Aconst unsigned ALTMODE = 0x008; 532292SN/A/** The request is to an uncacheable address. */ 541681SN/Aconst unsigned UNCACHEABLE = 0x010; 551060SN/A/** The request should not cause a page fault. */ 562980Sgblack@eecs.umich.educonst unsigned NO_FAULT = 0x020; 571060SN/A/** The request should be prefetched into the exclusive state. */ 586658Snate@binkert.orgconst unsigned PF_EXCLUSIVE = 0x100; 591717SN/A/** The request should be marked as LRU. */ 601717SN/Aconst unsigned EVICT_NEXT = 0x200; 612292SN/A/** The request should ignore unaligned access faults */ 622292SN/Aconst unsigned NO_ALIGN_FAULT = 0x400; 638229Snate@binkert.org 648229Snate@binkert.orgclass Request 658229Snate@binkert.org{ 668229Snate@binkert.org //@todo Make Accesor functions, make these private. 672817Sksewell@umich.edu public: 688229Snate@binkert.org /** The physical address of the request. */ 691060SN/A Addr paddr; 701060SN/A 712316SN/A /** whether this req came from the CPU or not **DO we need this??***/ 722316SN/A bool nicReq; 732680Sktlim@umich.edu 742817Sksewell@umich.edu /** The size of the request. */ 752817Sksewell@umich.edu int size; 762843Sktlim@umich.edu 772843Sktlim@umich.edu /** The time this request was started. Used to calculate latencies. */ 782669Sktlim@umich.edu Tick time; 791060SN/A 801060SN/A /** Destination address if this is a block copy. */ 818737Skoansin.tan@gmail.com Addr copyDest; 825529Snate@binkert.org 832733Sktlim@umich.edu uint32_t flags; 841060SN/A}; 851060SN/A 861060SN/Aclass CpuRequest : public Request 875529Snate@binkert.org{ 882292SN/A //@todo Make Accesor functions, make these private. 892292SN/A public: 901060SN/A /** The virtual address of the request. */ 911060SN/A Addr vaddr; 922348SN/A 932348SN/A /** The address space ID. */ 942348SN/A int asid; 952348SN/A 962348SN/A /** The return value of store conditional. */ 971060SN/A uint64_t scResult; 982733Sktlim@umich.edu 991060SN/A /** The cpu number for statistics. */ 1001060SN/A int cpuNum; 1012325SN/A 1021060SN/A /** The requesting thread id. */ 1031061SN/A int threadNum; 1044329Sktlim@umich.edu 1051060SN/A /** program counter of initiating access; for tracing/debugging */ 1065595Sgblack@eecs.umich.edu Addr pc; 1072292SN/A}; 1082292SN/A 1092292SN/A#endif // __MEM_REQUEST_HH__ 1102292SN/A