request.hh revision 2495 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @file Decleration of a request, the overall memory request consisting of
31 the parts of the request that are persistent throughout the transaction.
32 */
33
34#ifndef __MEM_REQUEST_HH__
35#define __MEM_REQUEST_HH__
36
37#include "arch/isa_traits.hh"
38
39class Request;
40class CpuRequest;
41
42typedef Request* RequestPtr;
43typedef CpuRequest* CpuRequestPtr;
44
45/** The request is a Load locked/store conditional. */
46const unsigned LOCKED		= 0x001;
47/** The virtual address is also the physical address. */
48const unsigned PHYSICAL		= 0x002;
49/** The request is an ALPHA VPTE pal access (hw_ld). */
50const unsigned VPTE		= 0x004;
51/** Use the alternate mode bits in ALPHA. */
52const unsigned ALTMODE		= 0x008;
53/** The request is to an uncacheable address. */
54const unsigned UNCACHEABLE	= 0x010;
55/** The request should not cause a page fault. */
56const unsigned NO_FAULT         = 0x020;
57/** The request should be prefetched into the exclusive state. */
58const unsigned PF_EXCLUSIVE	= 0x100;
59/** The request should be marked as LRU. */
60const unsigned EVICT_NEXT	= 0x200;
61/** The request should ignore unaligned access faults */
62const unsigned NO_ALIGN_FAULT   = 0x400;
63
64class Request
65{
66    //@todo Make Accesor functions, make these private.
67  public:
68    /** The physical address of the request. */
69    Addr paddr;
70
71    /** whether this req came from the CPU or not  **DO we need this??***/
72    bool nicReq;
73
74    /** The size of the request. */
75    int size;
76
77    /** The time this request was started. Used to calculate latencies. */
78    Tick time;
79
80    /** Destination address if this is a block copy. */
81    Addr copyDest;
82
83    uint32_t flags;
84};
85
86class CpuRequest : public Request
87{
88    //@todo Make Accesor functions, make these private.
89  public:
90    /** The virtual address of the request. */
91    Addr vaddr;
92
93    /** The address space ID. */
94    int asid;
95
96    /** The return value of store conditional. */
97    uint64_t scResult;
98
99    /** The cpu number for statistics. */
100    int cpuNum;
101
102    /** The requesting  thread id. */
103    int  threadNum;
104
105    /** program counter of initiating access; for tracing/debugging */
106    Addr pc;
107};
108
109#endif // __MEM_REQUEST_HH__
110