turnaround_policy_ideal.cc revision 12968
112968Sgiacomo.travaglini@arm.com/* 212968Sgiacomo.travaglini@arm.com * Copyright (c) 2018 ARM Limited 312968Sgiacomo.travaglini@arm.com * All rights reserved 412968Sgiacomo.travaglini@arm.com * 512968Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612968Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712968Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812968Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912968Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012968Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112968Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212968Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312968Sgiacomo.travaglini@arm.com * 1412968Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512968Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612968Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712968Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812968Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912968Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012968Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112968Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212968Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312968Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412968Sgiacomo.travaglini@arm.com * 2512968Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612968Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712968Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812968Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912968Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012968Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112968Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212968Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312968Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412968Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512968Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612968Sgiacomo.travaglini@arm.com * 3712968Sgiacomo.travaglini@arm.com * Authors: Matteo Andreozzi 3812968Sgiacomo.travaglini@arm.com */ 3912968Sgiacomo.travaglini@arm.com 4012968Sgiacomo.travaglini@arm.com#include "turnaround_policy_ideal.hh" 4112968Sgiacomo.travaglini@arm.com 4212968Sgiacomo.travaglini@arm.com#include "params/QoSTurnaroundPolicyIdeal.hh" 4312968Sgiacomo.travaglini@arm.com 4412968Sgiacomo.travaglini@arm.comnamespace QoS { 4512968Sgiacomo.travaglini@arm.com 4612968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::TurnaroundPolicyIdeal(const Params* p) 4712968Sgiacomo.travaglini@arm.com : TurnaroundPolicy(p) 4812968Sgiacomo.travaglini@arm.com{} 4912968Sgiacomo.travaglini@arm.com 5012968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::~TurnaroundPolicyIdeal() 5112968Sgiacomo.travaglini@arm.com{} 5212968Sgiacomo.travaglini@arm.com 5312968Sgiacomo.travaglini@arm.comMemCtrl::BusState 5412968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::selectBusState() 5512968Sgiacomo.travaglini@arm.com{ 5612968Sgiacomo.travaglini@arm.com auto bus_state = memCtrl->getBusState(); 5712968Sgiacomo.travaglini@arm.com const auto num_priorities = memCtrl->numPriorities(); 5812968Sgiacomo.travaglini@arm.com 5912968Sgiacomo.travaglini@arm.com // QoS-aware turnaround policy 6012968Sgiacomo.travaglini@arm.com // Loop for every queue in the memory controller. 6112968Sgiacomo.travaglini@arm.com for (uint8_t i = 0; i < num_priorities; i++) { 6212968Sgiacomo.travaglini@arm.com 6312968Sgiacomo.travaglini@arm.com // Starting from top priority queues first 6412968Sgiacomo.travaglini@arm.com uint8_t queue_idx = num_priorities - i - 1; 6512968Sgiacomo.travaglini@arm.com 6612968Sgiacomo.travaglini@arm.com const uint64_t readq_size = memCtrl->getReadQueueSize(queue_idx); 6712968Sgiacomo.travaglini@arm.com const uint64_t writeq_size = memCtrl->getWriteQueueSize(queue_idx); 6812968Sgiacomo.travaglini@arm.com 6912968Sgiacomo.travaglini@arm.com // No data for current priority: both the read queue 7012968Sgiacomo.travaglini@arm.com // and write queue are empty. 7112968Sgiacomo.travaglini@arm.com if ((readq_size == 0) && (writeq_size == 0)) { 7212968Sgiacomo.travaglini@arm.com continue; 7312968Sgiacomo.travaglini@arm.com } 7412968Sgiacomo.travaglini@arm.com 7512968Sgiacomo.travaglini@arm.com // Data found - select state 7612968Sgiacomo.travaglini@arm.com if (readq_size == 0) { 7712968Sgiacomo.travaglini@arm.com bus_state = MemCtrl::WRITE; 7812968Sgiacomo.travaglini@arm.com } else if (writeq_size == 0) { 7912968Sgiacomo.travaglini@arm.com bus_state = MemCtrl::READ; 8012968Sgiacomo.travaglini@arm.com } else { 8112968Sgiacomo.travaglini@arm.com // readq_size > 0 && writeq_size > 0 8212968Sgiacomo.travaglini@arm.com bus_state = ((memCtrl->getBusState() == MemCtrl::READ) ? 8312968Sgiacomo.travaglini@arm.com MemCtrl::WRITE : MemCtrl::READ); 8412968Sgiacomo.travaglini@arm.com } 8512968Sgiacomo.travaglini@arm.com 8612968Sgiacomo.travaglini@arm.com DPRINTF(QOS, 8712968Sgiacomo.travaglini@arm.com "QoSMemoryTurnaround::QoSTurnaroundPolicyIdeal - " 8812968Sgiacomo.travaglini@arm.com "QoS priority %d queues %d, %d triggering bus %s " 8912968Sgiacomo.travaglini@arm.com "in state %s\n", queue_idx, readq_size, writeq_size, 9012968Sgiacomo.travaglini@arm.com (bus_state != memCtrl->getBusState()) ? 9112968Sgiacomo.travaglini@arm.com "turnaround" : "staying", 9212968Sgiacomo.travaglini@arm.com (bus_state == MemCtrl::READ)? "READ" : "WRITE"); 9312968Sgiacomo.travaglini@arm.com // State selected - exit loop 9412968Sgiacomo.travaglini@arm.com break; 9512968Sgiacomo.travaglini@arm.com } 9612968Sgiacomo.travaglini@arm.com 9712968Sgiacomo.travaglini@arm.com return bus_state; 9812968Sgiacomo.travaglini@arm.com} 9912968Sgiacomo.travaglini@arm.com 10012968Sgiacomo.travaglini@arm.com} // namespace QoS 10112968Sgiacomo.travaglini@arm.com 10212968Sgiacomo.travaglini@arm.comQoS::TurnaroundPolicyIdeal * 10312968Sgiacomo.travaglini@arm.comQoSTurnaroundPolicyIdealParams::create() 10412968Sgiacomo.travaglini@arm.com{ 10512968Sgiacomo.travaglini@arm.com return new QoS::TurnaroundPolicyIdeal(this); 10612968Sgiacomo.travaglini@arm.com} 107