physical.cc revision 4626
12391SN/A/* 22391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32391SN/A * All rights reserved. 42391SN/A * 52391SN/A * Redistribution and use in source and binary forms, with or without 62391SN/A * modification, are permitted provided that the following conditions are 72391SN/A * met: redistributions of source code must retain the above copyright 82391SN/A * notice, this list of conditions and the following disclaimer; 92391SN/A * redistributions in binary form must reproduce the above copyright 102391SN/A * notice, this list of conditions and the following disclaimer in the 112391SN/A * documentation and/or other materials provided with the distribution; 122391SN/A * neither the name of the copyright holders nor the names of its 132391SN/A * contributors may be used to endorse or promote products derived from 142391SN/A * this software without specific prior written permission. 152391SN/A * 162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292914Ssaidi@eecs.umich.edu * Ali Saidi 302391SN/A */ 312391SN/A 322391SN/A#include <sys/types.h> 332391SN/A#include <sys/mman.h> 342391SN/A#include <errno.h> 352391SN/A#include <fcntl.h> 362391SN/A#include <unistd.h> 372391SN/A#include <zlib.h> 382391SN/A 392391SN/A#include <iostream> 402391SN/A#include <string> 412391SN/A 423348Sbinkertn@umich.edu#include "arch/isa_traits.hh" 432391SN/A#include "base/misc.hh" 442391SN/A#include "config/full_system.hh" 453879Ssaidi@eecs.umich.edu#include "mem/packet_access.hh" 462394SN/A#include "mem/physical.hh" 472391SN/A#include "sim/builder.hh" 482415SN/A#include "sim/eventq.hh" 493348Sbinkertn@umich.edu#include "sim/host.hh" 502394SN/A 512391SN/Ausing namespace std; 522423SN/Ausing namespace TheISA; 532391SN/A 543012Ssaidi@eecs.umich.eduPhysicalMemory::PhysicalMemory(Params *p) 554467Sstever@eecs.umich.edu : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p) 562391SN/A{ 573012Ssaidi@eecs.umich.edu if (params()->addrRange.size() % TheISA::PageBytes != 0) 582391SN/A panic("Memory Size not divisible by page size\n"); 592391SN/A 602391SN/A int map_flags = MAP_ANON | MAP_PRIVATE; 614626Sstever@eecs.umich.edu pmemAddr = 624626Sstever@eecs.umich.edu (uint8_t *)mmap(NULL, params()->addrRange.size(), 634626Sstever@eecs.umich.edu PROT_READ | PROT_WRITE, map_flags, -1, 0); 642391SN/A 653012Ssaidi@eecs.umich.edu if (pmemAddr == (void *)MAP_FAILED) { 662391SN/A perror("mmap"); 672391SN/A fatal("Could not mmap!\n"); 682391SN/A } 692391SN/A 703751Sgblack@eecs.umich.edu //If requested, initialize all the memory to 0 713751Sgblack@eecs.umich.edu if(params()->zero) 723751Sgblack@eecs.umich.edu memset(pmemAddr, 0, params()->addrRange.size()); 733751Sgblack@eecs.umich.edu 743012Ssaidi@eecs.umich.edu pagePtr = 0; 752391SN/A} 762391SN/A 772541SN/Avoid 782541SN/APhysicalMemory::init() 792541SN/A{ 804470Sstever@eecs.umich.edu if (ports.size() == 0) { 814470Sstever@eecs.umich.edu fatal("PhysicalMemory object %s is unconnected!", name()); 824470Sstever@eecs.umich.edu } 834470Sstever@eecs.umich.edu 844467Sstever@eecs.umich.edu for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { 854467Sstever@eecs.umich.edu if (*pi) 864467Sstever@eecs.umich.edu (*pi)->sendStatusChange(Port::RangeChange); 874467Sstever@eecs.umich.edu } 882541SN/A} 892541SN/A 902391SN/APhysicalMemory::~PhysicalMemory() 912391SN/A{ 923012Ssaidi@eecs.umich.edu if (pmemAddr) 933918Ssaidi@eecs.umich.edu munmap((char*)pmemAddr, params()->addrRange.size()); 942416SN/A //Remove memPorts? 952391SN/A} 962391SN/A 972391SN/AAddr 982391SN/APhysicalMemory::new_page() 992391SN/A{ 1003012Ssaidi@eecs.umich.edu Addr return_addr = pagePtr << LogVMPageSize; 1014040Ssaidi@eecs.umich.edu return_addr += start(); 1022391SN/A 1033012Ssaidi@eecs.umich.edu ++pagePtr; 1042391SN/A return return_addr; 1052391SN/A} 1062391SN/A 1072408SN/Aint 1082408SN/APhysicalMemory::deviceBlockSize() 1092408SN/A{ 1102409SN/A //Can accept anysize request 1112409SN/A return 0; 1122408SN/A} 1132408SN/A 1143012Ssaidi@eecs.umich.eduTick 1153349Sbinkertn@umich.eduPhysicalMemory::calculateLatency(PacketPtr pkt) 1163012Ssaidi@eecs.umich.edu{ 1173012Ssaidi@eecs.umich.edu return lat; 1183012Ssaidi@eecs.umich.edu} 1192413SN/A 1203170Sstever@eecs.umich.edu 1213170Sstever@eecs.umich.edu 1223170Sstever@eecs.umich.edu// Add load-locked to tracking list. Should only be called if the 1233170Sstever@eecs.umich.edu// operation is a load and the LOCKED flag is set. 1243170Sstever@eecs.umich.eduvoid 1254626Sstever@eecs.umich.eduPhysicalMemory::trackLoadLocked(PacketPtr pkt) 1263170Sstever@eecs.umich.edu{ 1274626Sstever@eecs.umich.edu Request *req = pkt->req; 1283170Sstever@eecs.umich.edu Addr paddr = LockedAddr::mask(req->getPaddr()); 1293170Sstever@eecs.umich.edu 1303170Sstever@eecs.umich.edu // first we check if we already have a locked addr for this 1313170Sstever@eecs.umich.edu // xc. Since each xc only gets one, we just update the 1323170Sstever@eecs.umich.edu // existing record with the new address. 1333170Sstever@eecs.umich.edu list<LockedAddr>::iterator i; 1343170Sstever@eecs.umich.edu 1353170Sstever@eecs.umich.edu for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 1363170Sstever@eecs.umich.edu if (i->matchesContext(req)) { 1373170Sstever@eecs.umich.edu DPRINTF(LLSC, "Modifying lock record: cpu %d thread %d addr %#x\n", 1383170Sstever@eecs.umich.edu req->getCpuNum(), req->getThreadNum(), paddr); 1393170Sstever@eecs.umich.edu i->addr = paddr; 1403170Sstever@eecs.umich.edu return; 1413170Sstever@eecs.umich.edu } 1423170Sstever@eecs.umich.edu } 1433170Sstever@eecs.umich.edu 1443170Sstever@eecs.umich.edu // no record for this xc: need to allocate a new one 1453170Sstever@eecs.umich.edu DPRINTF(LLSC, "Adding lock record: cpu %d thread %d addr %#x\n", 1463170Sstever@eecs.umich.edu req->getCpuNum(), req->getThreadNum(), paddr); 1473170Sstever@eecs.umich.edu lockedAddrList.push_front(LockedAddr(req)); 1483170Sstever@eecs.umich.edu} 1493170Sstever@eecs.umich.edu 1503170Sstever@eecs.umich.edu 1513170Sstever@eecs.umich.edu// Called on *writes* only... both regular stores and 1523170Sstever@eecs.umich.edu// store-conditional operations. Check for conventional stores which 1533170Sstever@eecs.umich.edu// conflict with locked addresses, and for success/failure of store 1543170Sstever@eecs.umich.edu// conditionals. 1553170Sstever@eecs.umich.edubool 1564626Sstever@eecs.umich.eduPhysicalMemory::checkLockedAddrList(PacketPtr pkt) 1573170Sstever@eecs.umich.edu{ 1584626Sstever@eecs.umich.edu Request *req = pkt->req; 1593170Sstever@eecs.umich.edu Addr paddr = LockedAddr::mask(req->getPaddr()); 1604626Sstever@eecs.umich.edu bool isLocked = pkt->isLocked(); 1613170Sstever@eecs.umich.edu 1623170Sstever@eecs.umich.edu // Initialize return value. Non-conditional stores always 1633170Sstever@eecs.umich.edu // succeed. Assume conditional stores will fail until proven 1643170Sstever@eecs.umich.edu // otherwise. 1653170Sstever@eecs.umich.edu bool success = !isLocked; 1663170Sstever@eecs.umich.edu 1673170Sstever@eecs.umich.edu // Iterate over list. Note that there could be multiple matching 1683170Sstever@eecs.umich.edu // records, as more than one context could have done a load locked 1693170Sstever@eecs.umich.edu // to this location. 1703170Sstever@eecs.umich.edu list<LockedAddr>::iterator i = lockedAddrList.begin(); 1713170Sstever@eecs.umich.edu 1723170Sstever@eecs.umich.edu while (i != lockedAddrList.end()) { 1733170Sstever@eecs.umich.edu 1743170Sstever@eecs.umich.edu if (i->addr == paddr) { 1753170Sstever@eecs.umich.edu // we have a matching address 1763170Sstever@eecs.umich.edu 1773170Sstever@eecs.umich.edu if (isLocked && i->matchesContext(req)) { 1783170Sstever@eecs.umich.edu // it's a store conditional, and as far as the memory 1793170Sstever@eecs.umich.edu // system can tell, the requesting context's lock is 1803170Sstever@eecs.umich.edu // still valid. 1813170Sstever@eecs.umich.edu DPRINTF(LLSC, "StCond success: cpu %d thread %d addr %#x\n", 1823170Sstever@eecs.umich.edu req->getCpuNum(), req->getThreadNum(), paddr); 1833170Sstever@eecs.umich.edu success = true; 1843170Sstever@eecs.umich.edu } 1853170Sstever@eecs.umich.edu 1863170Sstever@eecs.umich.edu // Get rid of our record of this lock and advance to next 1873170Sstever@eecs.umich.edu DPRINTF(LLSC, "Erasing lock record: cpu %d thread %d addr %#x\n", 1883170Sstever@eecs.umich.edu i->cpuNum, i->threadNum, paddr); 1893170Sstever@eecs.umich.edu i = lockedAddrList.erase(i); 1903170Sstever@eecs.umich.edu } 1913170Sstever@eecs.umich.edu else { 1923170Sstever@eecs.umich.edu // no match: advance to next record 1933170Sstever@eecs.umich.edu ++i; 1943170Sstever@eecs.umich.edu } 1953170Sstever@eecs.umich.edu } 1963170Sstever@eecs.umich.edu 1973170Sstever@eecs.umich.edu if (isLocked) { 1984040Ssaidi@eecs.umich.edu req->setExtraData(success ? 1 : 0); 1993170Sstever@eecs.umich.edu } 2003170Sstever@eecs.umich.edu 2013170Sstever@eecs.umich.edu return success; 2023170Sstever@eecs.umich.edu} 2033170Sstever@eecs.umich.edu 2044626Sstever@eecs.umich.edu 2054626Sstever@eecs.umich.edu#if TRACING_ON 2064626Sstever@eecs.umich.edu 2074626Sstever@eecs.umich.edu#define CASE(A, T) \ 2084626Sstever@eecs.umich.edu case sizeof(T): \ 2094626Sstever@eecs.umich.edu DPRINTF(MemoryAccess, A " of size %i on address 0x%x data 0x%x\n", \ 2104626Sstever@eecs.umich.edu pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \ 2114626Sstever@eecs.umich.edu break 2124626Sstever@eecs.umich.edu 2134626Sstever@eecs.umich.edu 2144626Sstever@eecs.umich.edu#define TRACE_PACKET(A) \ 2154626Sstever@eecs.umich.edu do { \ 2164626Sstever@eecs.umich.edu switch (pkt->getSize()) { \ 2174626Sstever@eecs.umich.edu CASE(A, uint64_t); \ 2184626Sstever@eecs.umich.edu CASE(A, uint32_t); \ 2194626Sstever@eecs.umich.edu CASE(A, uint16_t); \ 2204626Sstever@eecs.umich.edu CASE(A, uint8_t); \ 2214626Sstever@eecs.umich.edu default: \ 2224626Sstever@eecs.umich.edu DPRINTF(MemoryAccess, A " of size %i on address 0x%x\n", \ 2234626Sstever@eecs.umich.edu pkt->getSize(), pkt->getAddr()); \ 2244626Sstever@eecs.umich.edu } \ 2254626Sstever@eecs.umich.edu } while (0) 2264626Sstever@eecs.umich.edu 2274626Sstever@eecs.umich.edu#else 2284626Sstever@eecs.umich.edu 2294626Sstever@eecs.umich.edu#define TRACE_PACKET(A) 2304626Sstever@eecs.umich.edu 2314626Sstever@eecs.umich.edu#endif 2324626Sstever@eecs.umich.edu 2334626Sstever@eecs.umich.eduTick 2344626Sstever@eecs.umich.eduPhysicalMemory::doAtomicAccess(PacketPtr pkt) 2352413SN/A{ 2364040Ssaidi@eecs.umich.edu assert(pkt->getAddr() >= start() && 2374040Ssaidi@eecs.umich.edu pkt->getAddr() + pkt->getSize() <= start() + size()); 2382414SN/A 2394626Sstever@eecs.umich.edu if (pkt->memInhibitAsserted()) { 2404626Sstever@eecs.umich.edu DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n", 2414626Sstever@eecs.umich.edu pkt->getAddr()); 2424626Sstever@eecs.umich.edu return 0; 2433175Srdreslin@umich.edu } 2444626Sstever@eecs.umich.edu 2454626Sstever@eecs.umich.edu uint8_t *hostAddr = pmemAddr + pkt->getAddr() - start(); 2464626Sstever@eecs.umich.edu 2474626Sstever@eecs.umich.edu if (pkt->cmd == MemCmd::SwapReq) { 2484040Ssaidi@eecs.umich.edu IntReg overwrite_val; 2494040Ssaidi@eecs.umich.edu bool overwrite_mem; 2504040Ssaidi@eecs.umich.edu uint64_t condition_val64; 2514040Ssaidi@eecs.umich.edu uint32_t condition_val32; 2524040Ssaidi@eecs.umich.edu 2534040Ssaidi@eecs.umich.edu assert(sizeof(IntReg) >= pkt->getSize()); 2544040Ssaidi@eecs.umich.edu 2554040Ssaidi@eecs.umich.edu overwrite_mem = true; 2564040Ssaidi@eecs.umich.edu // keep a copy of our possible write value, and copy what is at the 2574040Ssaidi@eecs.umich.edu // memory address into the packet 2584052Ssaidi@eecs.umich.edu std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize()); 2594626Sstever@eecs.umich.edu std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 2604040Ssaidi@eecs.umich.edu 2614040Ssaidi@eecs.umich.edu if (pkt->req->isCondSwap()) { 2624040Ssaidi@eecs.umich.edu if (pkt->getSize() == sizeof(uint64_t)) { 2634052Ssaidi@eecs.umich.edu condition_val64 = pkt->req->getExtraData(); 2644626Sstever@eecs.umich.edu overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 2654626Sstever@eecs.umich.edu sizeof(uint64_t)); 2664040Ssaidi@eecs.umich.edu } else if (pkt->getSize() == sizeof(uint32_t)) { 2674052Ssaidi@eecs.umich.edu condition_val32 = (uint32_t)pkt->req->getExtraData(); 2684626Sstever@eecs.umich.edu overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 2694626Sstever@eecs.umich.edu sizeof(uint32_t)); 2704040Ssaidi@eecs.umich.edu } else 2714040Ssaidi@eecs.umich.edu panic("Invalid size for conditional read/write\n"); 2724040Ssaidi@eecs.umich.edu } 2734040Ssaidi@eecs.umich.edu 2744040Ssaidi@eecs.umich.edu if (overwrite_mem) 2754626Sstever@eecs.umich.edu std::memcpy(hostAddr, &overwrite_val, pkt->getSize()); 2764040Ssaidi@eecs.umich.edu 2774626Sstever@eecs.umich.edu TRACE_PACKET("Read/Write"); 2784626Sstever@eecs.umich.edu } else if (pkt->isRead()) { 2794626Sstever@eecs.umich.edu assert(!pkt->isWrite()); 2804626Sstever@eecs.umich.edu if (pkt->isLocked()) { 2814626Sstever@eecs.umich.edu trackLoadLocked(pkt); 2824040Ssaidi@eecs.umich.edu } 2834626Sstever@eecs.umich.edu memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 2844626Sstever@eecs.umich.edu TRACE_PACKET("Read"); 2854626Sstever@eecs.umich.edu } else if (pkt->isWrite()) { 2864626Sstever@eecs.umich.edu if (writeOK(pkt)) { 2874626Sstever@eecs.umich.edu memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 2884626Sstever@eecs.umich.edu TRACE_PACKET("Write"); 2894626Sstever@eecs.umich.edu } 2904626Sstever@eecs.umich.edu } else if (pkt->isInvalidate()) { 2914626Sstever@eecs.umich.edu //upgrade or invalidate 2924626Sstever@eecs.umich.edu if (pkt->needsResponse()) { 2934626Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2944626Sstever@eecs.umich.edu } 2954040Ssaidi@eecs.umich.edu } else { 2962413SN/A panic("unimplemented"); 2972413SN/A } 2982420SN/A 2994626Sstever@eecs.umich.edu if (pkt->needsResponse()) { 3004626Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 3014626Sstever@eecs.umich.edu } 3024626Sstever@eecs.umich.edu return calculateLatency(pkt); 3034626Sstever@eecs.umich.edu} 3044626Sstever@eecs.umich.edu 3054626Sstever@eecs.umich.edu 3064626Sstever@eecs.umich.eduvoid 3074626Sstever@eecs.umich.eduPhysicalMemory::doFunctionalAccess(PacketPtr pkt) 3084626Sstever@eecs.umich.edu{ 3094626Sstever@eecs.umich.edu assert(pkt->getAddr() >= start() && 3104626Sstever@eecs.umich.edu pkt->getAddr() + pkt->getSize() <= start() + size()); 3114626Sstever@eecs.umich.edu 3124626Sstever@eecs.umich.edu uint8_t *hostAddr = pmemAddr + pkt->getAddr() - start(); 3134626Sstever@eecs.umich.edu 3144626Sstever@eecs.umich.edu if (pkt->cmd == MemCmd::ReadReq) { 3154626Sstever@eecs.umich.edu memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3164626Sstever@eecs.umich.edu TRACE_PACKET("Read"); 3174626Sstever@eecs.umich.edu } else if (pkt->cmd == MemCmd::WriteReq) { 3184626Sstever@eecs.umich.edu memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 3194626Sstever@eecs.umich.edu TRACE_PACKET("Write"); 3204626Sstever@eecs.umich.edu } else { 3214626Sstever@eecs.umich.edu panic("PhysicalMemory: unimplemented functional command %s", 3224626Sstever@eecs.umich.edu pkt->cmdString()); 3234626Sstever@eecs.umich.edu } 3244626Sstever@eecs.umich.edu 3252641Sstever@eecs.umich.edu pkt->result = Packet::Success; 3262413SN/A} 3272413SN/A 3284626Sstever@eecs.umich.edu 3292413SN/APort * 3302738Sstever@eecs.umich.eduPhysicalMemory::getPort(const std::string &if_name, int idx) 3312413SN/A{ 3324468Sstever@eecs.umich.edu // Accept request for "functional" port for backwards compatibility 3334468Sstever@eecs.umich.edu // with places where this function is called from C++. I'd prefer 3344468Sstever@eecs.umich.edu // to move all these into Python someday. 3354468Sstever@eecs.umich.edu if (if_name == "functional") { 3364468Sstever@eecs.umich.edu return new MemoryPort(csprintf("%s-functional", name()), this); 3374468Sstever@eecs.umich.edu } 3384468Sstever@eecs.umich.edu 3394467Sstever@eecs.umich.edu if (if_name != "port") { 3402462SN/A panic("PhysicalMemory::getPort: unknown port %s requested", if_name); 3412462SN/A } 3424467Sstever@eecs.umich.edu 3434467Sstever@eecs.umich.edu if (idx >= ports.size()) { 3444467Sstever@eecs.umich.edu ports.resize(idx+1); 3454467Sstever@eecs.umich.edu } 3464467Sstever@eecs.umich.edu 3474467Sstever@eecs.umich.edu if (ports[idx] != NULL) { 3484467Sstever@eecs.umich.edu panic("PhysicalMemory::getPort: port %d already assigned", idx); 3494467Sstever@eecs.umich.edu } 3504467Sstever@eecs.umich.edu 3514467Sstever@eecs.umich.edu MemoryPort *port = 3524467Sstever@eecs.umich.edu new MemoryPort(csprintf("%s-port%d", name(), idx), this); 3534467Sstever@eecs.umich.edu 3544467Sstever@eecs.umich.edu ports[idx] = port; 3554467Sstever@eecs.umich.edu return port; 3562413SN/A} 3572413SN/A 3584467Sstever@eecs.umich.edu 3592413SN/Avoid 3602413SN/APhysicalMemory::recvStatusChange(Port::Status status) 3612413SN/A{ 3622413SN/A} 3632413SN/A 3642640Sstever@eecs.umich.eduPhysicalMemory::MemoryPort::MemoryPort(const std::string &_name, 3652640Sstever@eecs.umich.edu PhysicalMemory *_memory) 3662914Ssaidi@eecs.umich.edu : SimpleTimingPort(_name), memory(_memory) 3672413SN/A{ } 3682413SN/A 3692413SN/Avoid 3702413SN/APhysicalMemory::MemoryPort::recvStatusChange(Port::Status status) 3712413SN/A{ 3722413SN/A memory->recvStatusChange(status); 3732413SN/A} 3742413SN/A 3752413SN/Avoid 3762522SN/APhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp, 3774475Sstever@eecs.umich.edu bool &snoop) 3782413SN/A{ 3792522SN/A memory->getAddressRanges(resp, snoop); 3802497SN/A} 3812497SN/A 3822497SN/Avoid 3834475Sstever@eecs.umich.eduPhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop) 3842497SN/A{ 3854475Sstever@eecs.umich.edu snoop = false; 3862522SN/A resp.clear(); 3874475Sstever@eecs.umich.edu resp.push_back(RangeSize(start(), params()->addrRange.size())); 3882413SN/A} 3892413SN/A 3902415SN/Aint 3912415SN/APhysicalMemory::MemoryPort::deviceBlockSize() 3922415SN/A{ 3932415SN/A return memory->deviceBlockSize(); 3942415SN/A} 3952413SN/A 3962413SN/ATick 3973349Sbinkertn@umich.eduPhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) 3982413SN/A{ 3994626Sstever@eecs.umich.edu return memory->doAtomicAccess(pkt); 4002413SN/A} 4012413SN/A 4022413SN/Avoid 4033349Sbinkertn@umich.eduPhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) 4042413SN/A{ 4054490Sstever@eecs.umich.edu checkFunctional(pkt); 4063612Srdreslin@umich.edu 4073091Sstever@eecs.umich.edu // Default implementation of SimpleTimingPort::recvFunctional() 4083091Sstever@eecs.umich.edu // calls recvAtomic() and throws away the latency; we can save a 4093091Sstever@eecs.umich.edu // little here by just not calculating the latency. 4102413SN/A memory->doFunctionalAccess(pkt); 4112413SN/A} 4122413SN/A 4132914Ssaidi@eecs.umich.eduunsigned int 4142914Ssaidi@eecs.umich.eduPhysicalMemory::drain(Event *de) 4152914Ssaidi@eecs.umich.edu{ 4164467Sstever@eecs.umich.edu int count = 0; 4174467Sstever@eecs.umich.edu for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { 4184467Sstever@eecs.umich.edu count += (*pi)->drain(de); 4194467Sstever@eecs.umich.edu } 4204467Sstever@eecs.umich.edu 4212914Ssaidi@eecs.umich.edu if (count) 4222914Ssaidi@eecs.umich.edu changeState(Draining); 4232914Ssaidi@eecs.umich.edu else 4242914Ssaidi@eecs.umich.edu changeState(Drained); 4252914Ssaidi@eecs.umich.edu return count; 4262914Ssaidi@eecs.umich.edu} 4272413SN/A 4282391SN/Avoid 4292391SN/APhysicalMemory::serialize(ostream &os) 4302391SN/A{ 4312391SN/A gzFile compressedMem; 4322391SN/A string filename = name() + ".physmem"; 4332391SN/A 4342391SN/A SERIALIZE_SCALAR(filename); 4352391SN/A 4362391SN/A // write memory file 4372391SN/A string thefile = Checkpoint::dir() + "/" + filename.c_str(); 4382391SN/A int fd = creat(thefile.c_str(), 0664); 4392391SN/A if (fd < 0) { 4402391SN/A perror("creat"); 4412391SN/A fatal("Can't open physical memory checkpoint file '%s'\n", filename); 4422391SN/A } 4432391SN/A 4442391SN/A compressedMem = gzdopen(fd, "wb"); 4452391SN/A if (compressedMem == NULL) 4462391SN/A fatal("Insufficient memory to allocate compression state for %s\n", 4472391SN/A filename); 4482391SN/A 4493012Ssaidi@eecs.umich.edu if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) { 4502391SN/A fatal("Write failed on physical memory checkpoint file '%s'\n", 4512391SN/A filename); 4522391SN/A } 4532391SN/A 4542391SN/A if (gzclose(compressedMem)) 4552391SN/A fatal("Close failed on physical memory checkpoint file '%s'\n", 4562391SN/A filename); 4572391SN/A} 4582391SN/A 4592391SN/Avoid 4602391SN/APhysicalMemory::unserialize(Checkpoint *cp, const string §ion) 4612391SN/A{ 4622391SN/A gzFile compressedMem; 4632391SN/A long *tempPage; 4642391SN/A long *pmem_current; 4652391SN/A uint64_t curSize; 4662391SN/A uint32_t bytesRead; 4672391SN/A const int chunkSize = 16384; 4682391SN/A 4692391SN/A 4702391SN/A string filename; 4712391SN/A 4722391SN/A UNSERIALIZE_SCALAR(filename); 4732391SN/A 4742391SN/A filename = cp->cptDir + "/" + filename; 4752391SN/A 4762391SN/A // mmap memoryfile 4772391SN/A int fd = open(filename.c_str(), O_RDONLY); 4782391SN/A if (fd < 0) { 4792391SN/A perror("open"); 4802391SN/A fatal("Can't open physical memory checkpoint file '%s'", filename); 4812391SN/A } 4822391SN/A 4832391SN/A compressedMem = gzdopen(fd, "rb"); 4842391SN/A if (compressedMem == NULL) 4852391SN/A fatal("Insufficient memory to allocate compression state for %s\n", 4862391SN/A filename); 4872391SN/A 4883012Ssaidi@eecs.umich.edu // unmap file that was mmaped in the constructor 4893012Ssaidi@eecs.umich.edu // This is done here to make sure that gzip and open don't muck with our 4903012Ssaidi@eecs.umich.edu // nice large space of memory before we reallocate it 4913918Ssaidi@eecs.umich.edu munmap((char*)pmemAddr, params()->addrRange.size()); 4922391SN/A 4933012Ssaidi@eecs.umich.edu pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, 4942391SN/A MAP_ANON | MAP_PRIVATE, -1, 0); 4952391SN/A 4963012Ssaidi@eecs.umich.edu if (pmemAddr == (void *)MAP_FAILED) { 4972391SN/A perror("mmap"); 4982391SN/A fatal("Could not mmap physical memory!\n"); 4992391SN/A } 5002391SN/A 5012391SN/A curSize = 0; 5022391SN/A tempPage = (long*)malloc(chunkSize); 5032391SN/A if (tempPage == NULL) 5042391SN/A fatal("Unable to malloc memory to read file %s\n", filename); 5052391SN/A 5062391SN/A /* Only copy bytes that are non-zero, so we don't give the VM system hell */ 5073012Ssaidi@eecs.umich.edu while (curSize < params()->addrRange.size()) { 5082391SN/A bytesRead = gzread(compressedMem, tempPage, chunkSize); 5093012Ssaidi@eecs.umich.edu if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize) 5102391SN/A fatal("Read failed on physical memory checkpoint file '%s'" 5112391SN/A " got %d bytes, expected %d or %d bytes\n", 5123012Ssaidi@eecs.umich.edu filename, bytesRead, chunkSize, params()->addrRange.size()-curSize); 5132391SN/A 5142391SN/A assert(bytesRead % sizeof(long) == 0); 5152391SN/A 5162391SN/A for (int x = 0; x < bytesRead/sizeof(long); x++) 5172391SN/A { 5182391SN/A if (*(tempPage+x) != 0) { 5193012Ssaidi@eecs.umich.edu pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long)); 5202391SN/A *pmem_current = *(tempPage+x); 5212391SN/A } 5222391SN/A } 5232391SN/A curSize += bytesRead; 5242391SN/A } 5252391SN/A 5262391SN/A free(tempPage); 5272391SN/A 5282391SN/A if (gzclose(compressedMem)) 5292391SN/A fatal("Close failed on physical memory checkpoint file '%s'\n", 5302391SN/A filename); 5312391SN/A 5322391SN/A} 5332391SN/A 5342413SN/A 5352391SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) 5362391SN/A 5372391SN/A Param<string> file; 5382391SN/A Param<Range<Addr> > range; 5392565SN/A Param<Tick> latency; 5403751Sgblack@eecs.umich.edu Param<bool> zero; 5412391SN/A 5422391SN/AEND_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) 5432391SN/A 5442391SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) 5452391SN/A 5462391SN/A INIT_PARAM_DFLT(file, "memory mapped file", ""), 5472565SN/A INIT_PARAM(range, "Device Address Range"), 5483751Sgblack@eecs.umich.edu INIT_PARAM(latency, "Memory access latency"), 5493751Sgblack@eecs.umich.edu INIT_PARAM(zero, "Zero initialize memory") 5502391SN/A 5512391SN/AEND_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) 5522391SN/A 5532391SN/ACREATE_SIM_OBJECT(PhysicalMemory) 5542391SN/A{ 5553012Ssaidi@eecs.umich.edu PhysicalMemory::Params *p = new PhysicalMemory::Params; 5563012Ssaidi@eecs.umich.edu p->name = getInstanceName(); 5573012Ssaidi@eecs.umich.edu p->addrRange = range; 5583012Ssaidi@eecs.umich.edu p->latency = latency; 5593751Sgblack@eecs.umich.edu p->zero = zero; 5603012Ssaidi@eecs.umich.edu return new PhysicalMemory(p); 5612391SN/A} 5622391SN/A 5632391SN/AREGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory) 564