fs_translating_port_proxy.hh revision 8229
12030SN/A/* 22030SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32054SN/A * All rights reserved. 42054SN/A * 52054SN/A * Redistribution and use in source and binary forms, with or without 62054SN/A * modification, are permitted provided that the following conditions are 72054SN/A * met: redistributions of source code must retain the above copyright 82054SN/A * notice, this list of conditions and the following disclaimer; 92054SN/A * redistributions in binary form must reproduce the above copyright 102054SN/A * notice, this list of conditions and the following disclaimer in the 112054SN/A * documentation and/or other materials provided with the distribution; 122054SN/A * neither the name of the copyright holders nor the names of its 132054SN/A * contributors may be used to endorse or promote products derived from 142054SN/A * this software without specific prior written permission. 152054SN/A * 162054SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172054SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182054SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192054SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202054SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212054SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222054SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232054SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242054SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252054SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262054SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272054SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 293377Sgblack@eecs.umich.edu */ 302030SN/A 312649Ssaidi@eecs.umich.edu/** 322649Ssaidi@eecs.umich.edu * @file 332649Ssaidi@eecs.umich.edu * Virtual Port Object Declaration. These ports incorporate some translation 342649Ssaidi@eecs.umich.edu * into their access methods. Thus you can use one to read and write data 352649Ssaidi@eecs.umich.edu * to/from virtual addresses. 362649Ssaidi@eecs.umich.edu */ 372649Ssaidi@eecs.umich.edu 382504SN/A#ifndef __MEM_VPORT_HH__ 392030SN/A#define __MEM_VPORT_HH__ 402030SN/A 412030SN/A#include "arch/vtophys.hh" 422030SN/A#include "config/full_system.hh" 432030SN/A#include "mem/port_impl.hh" 442030SN/A 452030SN/A/** A class that translates a virtual address to a physical address and then 462030SN/A * calls the above read/write functions. If a thread context is provided the 472030SN/A * address can alway be translated, If not it can only be translated if it is a 482030SN/A * simple address masking operation (such as alpha super page accesses). 492504SN/A */ 502030SN/A 512030SN/A 522504SN/Aclass VirtualPort : public FunctionalPort 532030SN/A{ 542030SN/A private: 552504SN/A ThreadContext *tc; 562030SN/A 572030SN/A public: 582504SN/A VirtualPort(const std::string &_name, ThreadContext *_tc = NULL) 592030SN/A : FunctionalPort(_name), tc(_tc) 602030SN/A {} 612504SN/A 62 /** Return true if we have an thread context. This is used to 63 * prevent someone from accidently deleting the cpus statically 64 * allocated vport. 65 * @return true if a thread context isn't valid 66 */ 67 bool nullThreadContext() { return tc != NULL; } 68 69 /** Version of readblob that translates virt->phys and deals 70 * with page boundries. */ 71 virtual void readBlob(Addr addr, uint8_t *p, int size); 72 73 /** Version of writeBlob that translates virt->phys and deals 74 * with page boundries. */ 75 virtual void writeBlob(Addr addr, uint8_t *p, int size); 76}; 77 78 79void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen); 80void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen); 81void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); 82void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); 83 84#endif //__MEM_VPORT_HH__ 85 86